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Threads 301 to 330 of 21963

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. send/receive data to/from fpga device

    Started by mahmood.n, 16th June 2017 09:24
    • Replies: 11
    • Views: 1,331
    17th June 2017, 09:32 Go to last post
    • Replies: 4
    • Views: 556
    17th June 2017, 00:42 Go to last post
  2. Single multiplier takes up a whole DSP block for

    Started by shaiko, 14th June 2017 15:51
    • Replies: 13
    • Views: 1,145
    16th June 2017, 08:54 Go to last post
  3. Quartus not show the port size correctly

    Started by mahmood.n, 15th June 2017 23:12
    • Replies: 2
    • Views: 599
    16th June 2017, 07:43 Go to last post
  4. simulation-based faults injection

    Started by ouij, 12th June 2017 11:23
    • Replies: 7
    • Views: 919
    15th June 2017, 15:41 Go to last post
  5. binary dividing: restoring method

    Started by kk_0, 13th June 2017 20:32
    • Replies: 3
    • Views: 647
    14th June 2017, 22:22 Go to last post
    • Replies: 3
    • Views: 905
    14th June 2017, 18:01 Go to last post
  6. PWM for LED module to choose duty cycle

    Started by manush30, 28th May 2017 14:22
    • Replies: 6
    • Views: 1,074
    14th June 2017, 17:34 Go to last post
  7. Register vs BRAM vs slice count

    Started by Tarunfpga1, 13th June 2017 08:58
    • Replies: 1
    • Views: 446
    13th June 2017, 19:04 Go to last post
  8. How to work out with "inout" port in verilog?

    Started by hcu, 13th June 2017 06:41
    • Replies: 8
    • Views: 726
    13th June 2017, 18:46 Go to last post
  9. Temperature and Voltage Monitoring using XADC

    Started by beginner_EDA, 13th June 2017 14:29
    • Replies: 1
    • Views: 372
    13th June 2017, 16:16 Go to last post
    • Replies: 4
    • Views: 960
    13th June 2017, 16:13 Go to last post
  10. A pseudo-random number generator

    Started by Binome, 13th June 2017 10:25
    • Replies: 4
    • Views: 340
    13th June 2017, 14:15 Go to last post
  11. WARNING:NgdBuild:486 in xilinx

    Started by ecasha, 13th June 2017 04:25
    • Replies: 1
    • Views: 417
    13th June 2017, 08:46 Go to last post
  12. [SOLVED] FPGA: Different behavior after synthesis

    Started by birbal, 12th June 2017 22:23
    • Replies: 4
    • Views: 537
    12th June 2017, 23:42 Go to last post
  13. Route 455: CLK Net may have excessive skew

    Started by sonika111, 12th June 2017 15:58
    • Replies: 1
    • Views: 428
    12th June 2017, 17:53 Go to last post
  14. I2C with Picoblaze processor

    Started by beginner_EDA, 7th June 2017 11:33
    • Replies: 2
    • Views: 723
    12th June 2017, 09:41 Go to last post
  15. [SOLVED] uart ip :: how to tranfer a register value from fpga to c code

    Started by dipin, 31st May 2017 14:34
    • Replies: 4
    • Views: 752
    12th June 2017, 07:59 Go to last post
  16. Using a component in loop

    Started by mahmood.n, 10th June 2017 10:34
    • Replies: 6
    • Views: 1,140
    11th June 2017, 14:20 Go to last post
  17. implementing a graph traversal algorithm on FPGA

    Started by doost4, 7th June 2017 10:16
    • Replies: 14
    • Views: 1,147
    9th June 2017, 15:39 Go to last post
  18. What to do with unused input pins

    Started by wesleytaylor, 7th June 2017 15:46
    • Replies: 3
    • Views: 586
    9th June 2017, 13:24 Go to last post
  19. Variable width data pulse generator

    Started by bit_an, 8th June 2017 23:09
    • Replies: 2
    • Views: 483
    9th June 2017, 00:33 Go to last post
    • Replies: 1
    • Views: 614
    8th June 2017, 17:22 Go to last post
    • Replies: 13
    • Views: 1,376
    7th June 2017, 12:22 Go to last post
  20. Fundamentals in Verilog

    Started by bit_an, 6th June 2017 18:05
    • Replies: 1
    • Views: 583
    6th June 2017, 18:31 Go to last post
  21. [moved] Slice count on FPGA ?

    Started by Tarunfpga1, 6th June 2017 17:20
    • Replies: 1
    • Views: 359
    6th June 2017, 17:47 Go to last post
    • Replies: 1
    • Views: 388
    6th June 2017, 16:52 Go to last post
  22. How to know the delay of Mult_add ?

    Started by happsky, 30th May 2017 08:21
    • Replies: 3
    • Views: 643
    6th June 2017, 07:40 Go to last post
    • Replies: 3
    • Views: 654
    5th June 2017, 07:22 Go to last post
  23. cypress usb not detected

    Started by Bosechandran, 27th December 2016 06:38
    • Replies: 2
    • Views: 1,002
    3rd June 2017, 17:02 Go to last post