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Threads 301 to 330 of 21779

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Efficient SerDes-Like Module

    Started by SharpWeapon, 7th April 2017 04:01
    • Replies: 4
    • Views: 308
    9th April 2017, 02:35 Go to last post
  2. using fixed point design in vivado SDK

    Started by sai_shashi, 5th April 2017 06:06
    • Replies: 3
    • Views: 300
    8th April 2017, 08:49 Go to last post
    • Replies: 4
    • Views: 310
    8th April 2017, 06:22 Go to last post
  3. Understanding types of IO pins on FPGAs

    Started by whack, 7th April 2017 11:04
    • Replies: 7
    • Views: 319
    8th April 2017, 05:51 Go to last post
  4. Need help with generating *INTERLACED* mode VGA signals

    Started by whack, 22nd March 2017 06:06
    2 Pages
    1 2
    • Replies: 28
    • Views: 863
    8th April 2017, 05:22 Go to last post
  5. Problems writing Verilog testbench for 4:1 mux

    Started by pakha, 4th April 2017 21:25
    • Replies: 8
    • Views: 490
    8th April 2017, 00:35 Go to last post
  6. IP modules missing in Vivado testbench

    Started by MOd24, 1st April 2017 11:28
    • Replies: 3
    • Views: 323
    6th April 2017, 20:52 Go to last post
  7. Modelsim error scfifo of altera is not bound

    Started by sonika111, 5th April 2017 13:17
    • Replies: 6
    • Views: 354
    6th April 2017, 17:11 Go to last post
  8. Verilog Simple Spi Code

    Started by Mucit23, 5th April 2017 09:50
    • Replies: 5
    • Views: 645
    6th April 2017, 16:56 Go to last post
  9. Block RAM using IPcore

    Started by emerson_11, 6th April 2017 06:06
    • Replies: 1
    • Views: 267
    6th April 2017, 10:30 Go to last post
  10. Low speed bank Clock pins

    Started by rayhh27, 21st March 2017 11:28
    • Replies: 9
    • Views: 484
    6th April 2017, 09:54 Go to last post
  11. [SOLVED] How to connect my adc code to XILINX AXI4 FIR IP

    Started by tsillen, 4th April 2017 17:10
    • Replies: 14
    • Views: 485
    6th April 2017, 08:25 Go to last post
    • Replies: 2
    • Views: 182
    6th April 2017, 07:46 Go to last post
    • Replies: 3
    • Views: 259
    5th April 2017, 17:12 Go to last post
  12. cordic for inverse trigonometry

    Started by reshmacv76, 30th March 2017 05:32
    • Replies: 5
    • Views: 344
    5th April 2017, 08:10 Go to last post
    • Replies: 0
    • Views: 161
    5th April 2017, 07:29 Go to last post
  13. Navigation through a path in Vivado

    Started by msdarvishi, 4th April 2017 20:58
    • Replies: 4
    • Views: 266
    5th April 2017, 00:43 Go to last post
    • Replies: 1
    • Views: 212
    4th April 2017, 14:49 Go to last post
  14. Stateless Module in HDL design

    Started by viyaaloth, 4th April 2017 10:34
    • Replies: 2
    • Views: 276
    4th April 2017, 11:09 Go to last post
    • Replies: 0
    • Views: 237
    4th April 2017, 06:14 Go to last post
  15. Verilog Hardware description language

    Started by pakha, 2nd April 2017 17:30
    • Replies: 4
    • Views: 373
    4th April 2017, 02:06 Go to last post
  16. Signal deleted in questasim

    Started by Binome, 3rd April 2017 10:42
    • Replies: 2
    • Views: 231
    3rd April 2017, 16:23 Go to last post
  17. fpga for solar inverter and power electronics

    Started by mshh, 2nd April 2017 11:50
    • Replies: 3
    • Views: 315
    3rd April 2017, 16:02 Go to last post
  18. BRAM Synthesis error - Xilinx ISE 14.7

    Started by DeepikaA, 3rd April 2017 08:24
    • Replies: 2
    • Views: 293
    3rd April 2017, 14:17 Go to last post
  19. How to read design output in Spartan 6 board?

    Started by doost4, 2nd April 2017 18:28
    • Replies: 5
    • Views: 400
    3rd April 2017, 14:10 Go to last post
  20. [SOLVED] Understanding set_input_delay And set_output_delay .SDC Constraints

    Started by FecP, 2nd April 2017 00:30
    • Replies: 1
    • Views: 327
    3rd April 2017, 03:00 Go to last post
  21. concatenating bits example

    Started by lh-, 1st April 2017 19:34
    • Replies: 2
    • Views: 277
    1st April 2017, 20:35 Go to last post
  22. what is the best way for replacing coding with vhdl

    Started by fahim1, 1st April 2017 12:47
    • Replies: 1
    • Views: 275
    1st April 2017, 14:30 Go to last post
  23. Unable to run C/RTL cosimulation in Vivado HLS

    Started by sai_shashi, 1st April 2017 07:32
    • Replies: 0
    • Views: 230
    1st April 2017, 07:32 Go to last post