1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    102,026
Page 11 of 736 FirstFirst ... 9 10 11 12 13 21 61 111 511 ... LastLast
Threads 301 to 330 of 22061

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. how to fix WARNING:Xst:1710

    Started by tanish, 12th August 2017 08:07
    • Replies: 1
    • Views: 356
    12th August 2017, 08:42 Go to last post
  2. optimized CDR settings for 12G-SDI

    Started by beginner_EDA, 10th August 2017 09:58
    • Replies: 1
    • Views: 466
    11th August 2017, 15:56 Go to last post
  3. VHDL Instantiation in modelSim

    Started by hareeshP, 10th August 2017 06:57
    • Replies: 14
    • Views: 893
    10th August 2017, 19:16 Go to last post
  4. Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
    • Replies: 2
    • Views: 597
    10th August 2017, 18:52 Go to last post
  5. ADC and DAC interface for Spartan - 3A

    Started by NJ176, 10th August 2017 11:02
    • Replies: 1
    • Views: 343
    10th August 2017, 13:13 Go to last post
    • Replies: 10
    • Views: 1,181
    9th August 2017, 06:27 Go to last post
  6. Same constant name in 2 different packages

    Started by shaiko, 5th August 2017 12:53
    • Replies: 11
    • Views: 1,275
    7th August 2017, 10:23 Go to last post
  7. FPGA timing due to Dist ram

    Started by Alauddin123, 6th August 2017 10:42
    • Replies: 1
    • Views: 504
    6th August 2017, 12:08 Go to last post
  8. use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 11
    • Views: 2,316
    4th August 2017, 23:04 Go to last post
  9. substitution for loops in design compiler

    Started by moonshine8995, 4th August 2017 11:04
    • Replies: 4
    • Views: 775
    4th August 2017, 18:02 Go to last post
  10. Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 949
    4th August 2017, 17:49 Go to last post
  11. [SOLVED] xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 691
    3rd August 2017, 20:53 Go to last post
    • Replies: 2
    • Views: 574
    3rd August 2017, 16:31 Go to last post
  12. Verilog Assignment code

    Started by hareeshP, 1st August 2017 10:23
    • Replies: 4
    • Views: 934
    2nd August 2017, 06:45 Go to last post
  13. VHDL Register transferring.

    Started by hareeshP, 19th July 2017 13:28
    • Replies: 15
    • Views: 1,264
    2nd August 2017, 06:15 Go to last post
  14. jtag uart speed problem

    Started by dipin, 1st August 2017 12:25
    • Replies: 1
    • Views: 685
    1st August 2017, 16:43 Go to last post
  15. FPGA interfacing ADC with sampling rate >150 Msps

    Started by sherif123, 31st July 2017 08:53
    • Replies: 4
    • Views: 733
    31st July 2017, 15:47 Go to last post
  16. [SOLVED] VHDL Equivalent of Verilog Code

    Started by hareeshP, 31st July 2017 12:44
    • Replies: 1
    • Views: 502
    31st July 2017, 13:59 Go to last post
  17. Need help for write code for recurrent block

    Started by Adnan86, 27th July 2017 21:24
    • Replies: 10
    • Views: 1,422
    30th July 2017, 17:15 Go to last post
    • Replies: 3
    • Views: 741
    29th July 2017, 17:32 Go to last post
  18. Closed: how to find area, latency, throughput, power in my design?

    Started by Reeyam, 25th June 2017 01:06
    • Replies: 19
    • Views: 1,900
    29th July 2017, 08:52 Go to last post
  19. Basic theory needed to learn FPGA

    Started by FootTea, 28th July 2017 08:52
    • Replies: 4
    • Views: 738
    29th July 2017, 00:47 Go to last post
  20. Closed: [moved] Input selector from two 8-bit digital port

    Started by jackobian, 3rd June 2017 12:39
    • Replies: 6
    • Views: 1,107
    28th July 2017, 07:24 Go to last post
  21. Closed: how to use generate&for to do "x = x + a(i)"

    Started by bravoegg, 26th July 2017 15:58
    • Replies: 10
    • Views: 796
    27th July 2017, 16:34 Go to last post
  22. Closed: LDPC: Bit-flipping decoding [Hard decision]

    Started by AbinayaSivam, 27th July 2017 08:30
    • Replies: 0
    • Views: 505
    27th July 2017, 08:30 Go to last post
  23. [SOLVED]Closed: qsys jtag_uart doubt

    Started by dipin, 25th July 2017 07:03
    • Replies: 7
    • Views: 878
    27th July 2017, 06:35 Go to last post
  24. Closed: Signal declaration based on a generic + VHDL

    Started by dpaul, 26th July 2017 13:20
    • Replies: 2
    • Views: 611
    26th July 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 534
    26th July 2017, 13:07 Go to last post
  25. Closed: measuring full system of network on chip performance

    Started by kian_mary, 26th July 2017 09:14
    • Replies: 0
    • Views: 351
    26th July 2017, 09:14 Go to last post