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Threads 301 to 330 of 22101

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Shift register will parallel load

    Started by sandy2811, 5th September 2017 13:17
    • Replies: 3
    • Views: 516
    8th September 2017, 15:26 Go to last post
  2. convert Floating point to fix point

    Started by linam, 7th September 2017 10:06
    • Replies: 6
    • Views: 537
    8th September 2017, 11:49 Go to last post
    • Replies: 1
    • Views: 317
    7th September 2017, 16:43 Go to last post
  3. very strange typecast (VHDL)

    Started by LatticeSemiconductor, 28th August 2017 10:57
    • Replies: 5
    • Views: 527
    7th September 2017, 13:13 Go to last post
  4. Counter Preload by any given values

    Started by sandy2811, 1st September 2017 07:55
    • Replies: 12
    • Views: 1,155
    7th September 2017, 06:12 Go to last post
  5. Strange behaviour of Standard dual-clock FIFO

    Started by Taki_comp, 3rd September 2017 14:19
    • Replies: 10
    • Views: 658
    4th September 2017, 08:18 Go to last post
  6. problem with VHDL mealy sequence detector

    Started by Armand86, 1st September 2017 21:47
    • Replies: 7
    • Views: 691
    2nd September 2017, 19:33 Go to last post
  7. How to design self checking testbench...

    Started by sandy2811, 22nd August 2017 13:10
    • Replies: 3
    • Views: 674
    2nd September 2017, 04:33 Go to last post
  8. Measuring the execution time on FPGA

    Started by doost4, 26th August 2017 18:39
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,378
    30th August 2017, 16:12 Go to last post
  9. Moved: Programmable Priority Encoder

    Started by RatedR, 29th August 2017 15:55
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  10. High level(P4) FPGA programming

    Started by beginner_EDA, 28th August 2017 23:43
    • Replies: 3
    • Views: 562
    29th August 2017, 10:07 Go to last post
  11. Closed: VHDL Testbench getting (U) in simulation waveform result

    Started by 12345r, 27th August 2017 18:04
    • Replies: 3
    • Views: 548
    28th August 2017, 09:35 Go to last post
  12. Closed: How to run de1 soc board using quartus tool or test bench?

    Started by liki102004, 22nd August 2017 07:23
    • Replies: 1
    • Views: 488
    27th August 2017, 23:19 Go to last post
  13. Closed: Critical path of combinational circuit

    Started by mahmood.n, 30th March 2017 13:11
    • Replies: 12
    • Views: 1,310
    26th August 2017, 23:10 Go to last post
  14. [SOLVED]Closed: Displaying grayscale video feed on HDMI

    Started by Taki_comp, 23rd August 2017 10:57
    • Replies: 2
    • Views: 504
    26th August 2017, 19:54 Go to last post
  15. [SOLVED]Closed: ORing even & odd bits of a vector

    Started by rahdirs, 26th August 2017 00:11
    • Replies: 1
    • Views: 445
    26th August 2017, 03:39 Go to last post
  16. Closed: Optical extention of a parallel bus

    Started by shaiko, 24th August 2017 15:14
    • Replies: 9
    • Views: 814
    25th August 2017, 18:03 Go to last post
  17. Closed: Hotswap in Vhdl using fpga

    Started by hareeshP, 21st August 2017 10:38
    • Replies: 6
    • Views: 616
    25th August 2017, 09:27 Go to last post
  18. [SOLVED]Closed: Processes and concurrent signal assignments

    Started by dzafar, 24th August 2017 00:57
    • Replies: 2
    • Views: 546
    25th August 2017, 08:25 Go to last post
    • Replies: 5
    • Views: 928
    24th August 2017, 09:50 Go to last post
  19. Closed: Use two separate codes in FPGA

    Started by NJ176, 21st August 2017 10:47
    • Replies: 7
    • Views: 908
    24th August 2017, 03:32 Go to last post
  20. Closed: How to configure UART for PL part of Zynq-7000 FPGA??

    Started by msdarvishi, 9th August 2017 00:30
    • Replies: 12
    • Views: 1,766
    23rd August 2017, 23:24 Go to last post
  21. Closed: Spartan - 3A ADC and DAC interface not working

    Started by NJ176, 15th August 2017 10:22
    • Replies: 8
    • Views: 723
    23rd August 2017, 19:14 Go to last post
  22. [SOLVED]Closed: Tcl to update version number

    Started by wesleytaylor, 18th August 2017 13:04
    • Replies: 6
    • Views: 784
    23rd August 2017, 16:33 Go to last post
  23. Closed: Cadence NCSIM Document

    Started by muthu7495, 22nd August 2017 13:04
    • Replies: 2
    • Views: 522
    22nd August 2017, 15:17 Go to last post
    • Replies: 1
    • Views: 409
    22nd August 2017, 13:29 Go to last post
  24. Closed: SuperCap in Xilinx Zynq

    Started by flote21, 22nd August 2017 07:35
    • Replies: 1
    • Views: 467
    22nd August 2017, 10:34 Go to last post
  25. Closed: Avery AXI_SLAVE warning

    Started by muthu7495, 21st August 2017 10:57
    • Replies: 3
    • Views: 457
    21st August 2017, 14:52 Go to last post