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Threads 3031 to 3060 of 22099

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: square root output in two clockcycle....

    Started by dipin, 27th October 2014 12:42
    • Replies: 15
    • Views: 1,181
    29th October 2014, 08:20 Go to last post
    • Replies: 3
    • Views: 1,797
    28th October 2014, 14:48 Go to last post
  2. Closed: is there any spice model for fpga?

    Started by Amin Khorsandi, 28th October 2014 08:57
    • Replies: 3
    • Views: 755
    28th October 2014, 14:05 Go to last post
  3. [SOLVED]Closed: cordic calculations of sine and cosine functions in fpga

    Started by brainiac_rus, 27th October 2014 16:05
    • Replies: 4
    • Views: 1,116
    28th October 2014, 10:38 Go to last post
  4. Closed: Bit flipping in SRAM

    Started by Manzar Mahmud, 28th October 2014 04:14
    • Replies: 0
    • Views: 631
    28th October 2014, 04:14 Go to last post
  5. Closed: if condition under fork funtion

    Started by mahalakshmi r, 27th October 2014 20:54
    • Replies: 2
    • Views: 441
    27th October 2014, 21:50 Go to last post
  6. Closed: Verilog Quad 7-seg display

    Started by Azaxa, 24th October 2014 21:15
    • Replies: 16
    • Views: 1,893
    27th October 2014, 18:20 Go to last post
    • Replies: 0
    • Views: 729
    27th October 2014, 16:29 Go to last post
  7. Closed: VHDL : Booth Multiplier Radix 4

    Started by karan123, 27th October 2014 13:30
    • Replies: 1
    • Views: 1,347
    27th October 2014, 16:09 Go to last post
  8. Closed: mulipler matrix in verilog

    Started by mohammadmother, 27th October 2014 14:47
    • Replies: 0
    • Views: 708
    27th October 2014, 14:47 Go to last post
  9. Closed: [moved] VHDL flash memory controller

    Started by shrutireddy, 27th October 2014 06:40
    • Replies: 1
    • Views: 662
    27th October 2014, 13:48 Go to last post
  10. Closed: Partial Reconfiguration and Scrubbing

    Started by msdarvishi, 25th October 2014 23:44
    • Replies: 3
    • Views: 810
    27th October 2014, 10:04 Go to last post
  11. Closed: FPGA in Altium. simple questions

    Started by Amin Khorsandi, 27th October 2014 06:16
    • Replies: 1
    • Views: 711
    27th October 2014, 09:26 Go to last post
  12. Closed: how to convert verilog into schematic in OS X?

    Started by simongu89, 21st October 2014 06:26
    • Replies: 3
    • Views: 1,246
    27th October 2014, 09:24 Go to last post
  13. [SOLVED]Closed: Tiny encription algorithm (TEA) in VHDL need help

    Started by emperror123, 26th October 2014 04:24
    • Replies: 6
    • Views: 1,456
    27th October 2014, 09:01 Go to last post
  14. Closed: Reversible Logic Gates Implementation in Tanner EDA

    Started by chandrapal1990, 27th October 2014 07:51
    • Replies: 0
    • Views: 746
    27th October 2014, 07:51 Go to last post
  15. Closed: Binning + Pipeline, How to do it, please?

    Started by flote21, 11th October 2014 16:38
    2 Pages
    1 2
    • Replies: 20
    • Views: 2,517
    27th October 2014, 06:35 Go to last post
  16. Closed: VHDL Synthesis Code help

    Started by Y.SAI SARASWATHI, 25th October 2014 16:05
    • Replies: 12
    • Views: 1,147
    27th October 2014, 05:43 Go to last post
  17. Closed: Frequency devider verilog code (50mhz to 75 micro second)

    Started by no0ona, 22nd October 2014 08:06
    • Replies: 7
    • Views: 1,123
    27th October 2014, 03:59 Go to last post
  18. [SOLVED]Closed: Need help on pipelining in square root using verilog

    Started by dipin, 15th October 2014 12:44
    • Replies: 14
    • Views: 2,617
    26th October 2014, 17:51 Go to last post
  19. Closed: Running 24bit adder at 128mhz, which FPGA to choose

    Started by ahgu, 24th October 2014 20:44
    • Replies: 15
    • Views: 1,409
    26th October 2014, 16:49 Go to last post
  20. Closed: vhdl code for an octal d-type flip flop register with clock enable

    Started by krisdan, 24th October 2014 15:12
    2 Pages
    1 2
    • Replies: 22
    • Views: 3,662
    26th October 2014, 16:45 Go to last post
  21. Closed: VHDL Simulators need help

    Started by Y.SAI SARASWATHI, 25th October 2014 15:44
    • Replies: 7
    • Views: 896
    26th October 2014, 16:11 Go to last post
  22. Closed: verilog code for turbo encoder and decoder

    Started by ksmb, 26th October 2014 08:42
    • Replies: 0
    • Views: 804
    26th October 2014, 08:42 Go to last post
  23. [SOLVED]Closed: Verilog for loop in test bench produces error in ModelSim

    Started by nervecell_23, 24th October 2014 12:07
    • Replies: 8
    • Views: 2,851
    24th October 2014, 18:06 Go to last post
  24. [SOLVED]Closed: Light-cycle game [HELP]

    Started by zilch, 24th October 2014 11:40
    • Replies: 0
    • Views: 415
    24th October 2014, 11:40 Go to last post
  25. Closed: Recomendation for a good VHDL book

    Started by flote21, 23rd October 2014 20:16
    • Replies: 2
    • Views: 1,355
    24th October 2014, 08:31 Go to last post
  26. Closed: mcf5272 coldfire programing?

    Started by arem, 23rd October 2014 22:49
    • Replies: 0
    • Views: 647
    23rd October 2014, 22:49 Go to last post
  27. Closed: Altera Qsys Generated Pci Express Wrapping

    Started by emrelevent, 23rd October 2014 18:31
    • Replies: 1
    • Views: 744
    23rd October 2014, 18:43 Go to last post
  28. Closed: [Moved] cascaded mux implementation using vhdl

    Started by rekhavp, 21st October 2014 09:28
    • Replies: 3
    • Views: 867
    22nd October 2014, 16:06 Go to last post