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Threads 3031 to 3060 of 21842

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: difference between FPGA and PLC

    Started by venkat25, 11th February 2009 07:43
    • Replies: 5
    • Views: 16,526
    16th August 2014, 01:35 Go to last post
  2. Closed: ROM design for BCD to Excess 3 converter

    Started by VPrasanth, 13th August 2014 11:15
    • Replies: 11
    • Views: 3,014
    14th August 2014, 18:42 Go to last post
  3. Closed: Sensitivity lists syntax in VHDL and Verilog

    Started by dstr, 12th August 2014 10:24
    • Replies: 13
    • Views: 2,121
    14th August 2014, 16:35 Go to last post
    • Replies: 0
    • Views: 1,109
    14th August 2014, 15:53 Go to last post
  4. Closed: Difference between blocking and nonblocking in Verilog

    Started by ruwan2, 7th August 2014 16:24
    • Replies: 9
    • Views: 1,181
    14th August 2014, 10:36 Go to last post
  5. Closed: Digital audio player with FPGA

    Started by andrea_mori, 14th August 2014 00:18
    • Replies: 3
    • Views: 885
    14th August 2014, 08:29 Go to last post
  6. Closed: What is CPLD XC9572XL

    Started by ep.hobbyiest, 10th August 2014 17:17
    • Replies: 6
    • Views: 865
    13th August 2014, 18:49 Go to last post
  7. [SOLVED]Closed: concurrent assignment

    Started by sumeet1990, 13th August 2014 16:24
    • Replies: 7
    • Views: 511
    13th August 2014, 18:18 Go to last post
  8. Closed: how to store image frames in memory

    Started by katayoon_1, 13th August 2014 12:09
    • Replies: 3
    • Views: 621
    13th August 2014, 15:54 Go to last post
  9. Closed: how to calculate leakage current.....

    Started by velu.plg, 12th August 2014 13:23
    • Replies: 2
    • Views: 857
    13th August 2014, 07:03 Go to last post
  10. Closed: control command in uhs-ii

    Started by kranthi_vlsi, 12th August 2014 14:01
    • Replies: 2
    • Views: 499
    13th August 2014, 02:34 Go to last post
  11. Closed: Modelsim signal subgroup visualization issue

    Started by zermelo, 12th August 2014 10:06
    • Replies: 0
    • Views: 501
    12th August 2014, 10:06 Go to last post
  12. Closed: Need used FPGA board

    Started by vamanan, 12th August 2014 01:59
    • Replies: 1
    • Views: 549
    12th August 2014, 02:45 Go to last post
  13. Closed: Timing issues in Xilinx and SmartXplorer

    Started by SharpWeapon, 11th August 2014 18:19
    • Replies: 4
    • Views: 911
    11th August 2014, 20:46 Go to last post
  14. Closed: [Moved] Required adder concepts with coding

    Started by lara24, 11th August 2014 18:50
    • Replies: 1
    • Views: 639
    11th August 2014, 20:17 Go to last post
  15. Closed: VHDL CODE Finding Max/Min of a sampled signal

    Started by tigag, 9th August 2014 22:09
    • Replies: 5
    • Views: 2,055
    10th August 2014, 21:30 Go to last post
  16. Closed: About my final year Project....

    Started by balamarimuthuhdl, 9th August 2014 08:05
    • Replies: 2
    • Views: 726
    9th August 2014, 11:28 Go to last post
  17. Closed: Is while loop in vhdl synthesizable

    Started by emmagood, 1st July 2014 04:05
    • Replies: 8
    • Views: 4,291
    9th August 2014, 00:10 Go to last post
  18. Closed: ISE run out of Memory

    Started by SharpWeapon, 7th August 2014 22:59
    • Replies: 4
    • Views: 2,006
    8th August 2014, 17:18 Go to last post
  19. Closed: [Moved] how to know how big is a asci/fpga design?

    Started by hjacky, 6th August 2014 03:10
    • Replies: 2
    • Views: 595
    8th August 2014, 16:19 Go to last post
  20. Closed: FPGA Development board selection

    Started by Maxxx54, 6th August 2014 18:42
    • Replies: 2
    • Views: 651
    8th August 2014, 15:53 Go to last post
    • Replies: 2
    • Views: 2,267
    8th August 2014, 13:21 Go to last post
  21. Closed: How to print '-4', not '11111111111100'

    Started by ruwan2, 8th August 2014 01:18
    • Replies: 4
    • Views: 653
    8th August 2014, 08:39 Go to last post
  22. Closed: Difference between LUT and MUX

    Started by Muthuraja.M, 6th August 2014 15:03
    • Replies: 6
    • Views: 1,361
    8th August 2014, 06:49 Go to last post
  23. Closed: Vivado warning during place design [Constraint 18-96]

    Started by wesleytaylor, 7th August 2014 17:54
    • Replies: 2
    • Views: 1,091
    8th August 2014, 06:41 Go to last post
  24. Closed: A print error with the description

    Started by ruwan2, 8th August 2014 01:28
    • Replies: 1
    • Views: 426
    8th August 2014, 01:50 Go to last post
  25. Closed: What is "the same bit pattern" in this sentence?

    Started by ruwan2, 8th August 2014 00:29
    • Replies: 0
    • Views: 497
    8th August 2014, 00:29 Go to last post
  26. [SOLVED]Closed: Why is power important in FPGA

    Started by arpitsodani, 27th July 2014 14:44
    • Replies: 5
    • Views: 632
    7th August 2014, 23:26 Go to last post
  27. Closed: FPGA Linear interpolator, problem in difference terms

    Started by zermelo, 6th August 2014 08:56
    • Replies: 6
    • Views: 716
    7th August 2014, 11:43 Go to last post
    • Replies: 2
    • Views: 890
    7th August 2014, 07:36 Go to last post