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Threads 3031 to 3060 of 21959

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: How to reduce usage of bonded IOBs

    Started by arishsu, 14th September 2014 12:16
    • Replies: 9
    • Views: 1,618
    18th September 2014, 16:19 Go to last post
  2. Closed: A few questions about Verilog

    Started by shaiko, 17th September 2014 07:36
    • Replies: 14
    • Views: 999
    17th September 2014, 22:23 Go to last post
  3. Closed: component instantiation and synthesis

    Started by shikharmakkar, 16th September 2014 02:08
    • Replies: 8
    • Views: 735
    17th September 2014, 18:41 Go to last post
  4. Closed: square root of a number

    Started by dipin, 17th September 2014 10:22
    • Replies: 3
    • Views: 836
    17th September 2014, 17:12 Go to last post
  5. Closed: cannot open macro file: system.do

    Started by mahound, 16th September 2014 18:05
    • Replies: 2
    • Views: 4,333
    17th September 2014, 16:28 Go to last post
  6. Closed: VHDL Program for a 4 bit full-adder

    Started by fm_com_28, 10th October 2006 21:33
    • Replies: 5
    • Views: 60,165
    17th September 2014, 09:24 Go to last post
  7. [SOLVED]Closed: Signed multiplier in Verilog. "signed" doesn't work

    Started by oak_tree, 15th September 2014 23:16
    • Replies: 6
    • Views: 1,214
    16th September 2014, 20:14 Go to last post
  8. Closed: 6 3phase motor speed inverter help

    Started by janosandi, 23rd July 2014 23:43
    • Replies: 7
    • Views: 736
    16th September 2014, 19:49 Go to last post
    • Replies: 1
    • Views: 476
    16th September 2014, 16:33 Go to last post
  9. [SOLVED]Closed: verilog: how to find max value in the bus

    Started by miskod, 16th September 2014 10:31
    • Replies: 1
    • Views: 771
    16th September 2014, 12:45 Go to last post
  10. [SOLVED]Closed: Suggestions for CISC and RISC cores for university use

    Started by dpaul, 12th September 2014 10:13
    • Replies: 2
    • Views: 438
    16th September 2014, 12:25 Go to last post
  11. [SOLVED]Closed: Matlab and Modelsim Cosimulation

    Started by sameh_yassin99, 31st October 2011 16:50
    • Replies: 7
    • Views: 4,652
    16th September 2014, 10:07 Go to last post
  12. Closed: Simulating a design with Altera PLL in modelsim

    Started by shaiko, 15th September 2014 11:09
    • Replies: 9
    • Views: 4,173
    15th September 2014, 23:54 Go to last post
  13. Closed: can anyone help me build a 5x5 bit signed multiplier

    Started by aishak_97, 15th September 2014 16:46
    • Replies: 2
    • Views: 1,023
    15th September 2014, 23:48 Go to last post
  14. Closed: Trying to run Nios LED code ?

    Started by bianchi77, 15th September 2014 12:57
    • Replies: 2
    • Views: 722
    15th September 2014, 22:26 Go to last post
  15. Closed: verilog code for input output

    Started by vead, 15th September 2014 16:03
    • Replies: 1
    • Views: 507
    15th September 2014, 16:12 Go to last post
  16. Closed: PLL- noisy powersupply tolerance

    Started by sakthivelmurugan, 15th September 2014 11:26
    • Replies: 1
    • Views: 420
    15th September 2014, 12:44 Go to last post
  17. Closed: VHDL resizing a string

    Started by shaiko, 13th September 2014 12:25
    • Replies: 11
    • Views: 2,014
    14th September 2014, 07:28 Go to last post
  18. Closed: VHDL 3D array input port

    Started by shaiko, 14th September 2014 01:23
    • Replies: 2
    • Views: 923
    14th September 2014, 07:21 Go to last post
  19. Closed: Image aquisition by camera to FPGA using GigE Vision or similar in speed

    Started by wolf12, 12th September 2014 03:52
    • Replies: 13
    • Views: 2,042
    14th September 2014, 07:20 Go to last post
  20. Closed: Altera Quad-Serial Configuration (EPCQ) Device

    Started by shaiko, 11th September 2014 08:47
    • Replies: 12
    • Views: 4,141
    13th September 2014, 11:51 Go to last post
  21. Moved: Real Time Clock in Seven Segment display

    Started by santh92, 13th September 2014 09:39
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  22. Closed: sync between clocks - interesting q

    Started by yuvalkesi, 11th September 2014 08:55
    • Replies: 3
    • Views: 554
    12th September 2014, 16:37 Go to last post
  23. Closed: Need help to simulate system c in Modelsim

    Started by Muthuraja.M, 11th September 2014 07:22
    • Replies: 3
    • Views: 823
    12th September 2014, 08:10 Go to last post
  24. [SOLVED]Closed: Simple code not working

    Started by bareil76, 10th September 2014 20:55
    • Replies: 5
    • Views: 539
    11th September 2014, 16:13 Go to last post
  25. Closed: HELP: code for number catcher(number select) implemented in FPGA

    Started by zilch, 11th September 2014 00:38
    • Replies: 10
    • Views: 914
    11th September 2014, 15:59 Go to last post
  26. Closed: majority logic decoder

    Started by bunty_22, 11th September 2014 11:26
    • Replies: 0
    • Views: 486
    11th September 2014, 11:26 Go to last post
  27. Closed: Using tcl console in vivado to open reports

    Started by wesleytaylor, 11th September 2014 09:57
    • Replies: 0
    • Views: 962
    11th September 2014, 09:57 Go to last post
  28. Closed: FPGA Beginners` Tutorials

    Started by jean12, 10th August 2014 18:55
    • Replies: 2
    • Views: 900
    11th September 2014, 04:55 Go to last post
  29. Closed: Are these lines usable?

    Started by FalloutBoy, 10th September 2014 15:18
    • Replies: 3
    • Views: 481
    10th September 2014, 18:17 Go to last post