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Threads 3001 to 3030 of 21880

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: 2 Dimensional FFT using 1 D in VHDL

    Started by shan14, 4th September 2014 11:19
    • Replies: 2
    • Views: 946
    5th September 2014, 13:24 Go to last post
  2. [SOLVED]Closed: NAND gates are faster?

    Started by kkdelabaca, 2nd September 2014 10:45
    • Replies: 6
    • Views: 868
    4th September 2014, 06:19 Go to last post
    • Replies: 1
    • Views: 495
    4th September 2014, 05:29 Go to last post
  3. [SOLVED]Closed: Virtex 6 Embedded Tri-mode Ethernet MAC wrapper interface

    Started by NIJIL N, 31st August 2014 12:27
    • Replies: 4
    • Views: 1,522
    4th September 2014, 05:01 Go to last post
  4. Closed: how to connect matrix keypad to a Cyclone FPGA

    Started by matrixofdynamism, 2nd September 2014 22:22
    • Replies: 5
    • Views: 1,481
    3rd September 2014, 20:11 Go to last post
  5. Closed: Map : 116 - The design is empty. No processing will be done

    Started by hassanzia, 22nd January 2013 17:42
    • Replies: 15
    • Views: 6,716
    3rd September 2014, 18:36 Go to last post
  6. [SOLVED]Closed: representation of negative fraction

    Started by dipin, 2nd September 2014 09:37
    • Replies: 10
    • Views: 926
    3rd September 2014, 15:52 Go to last post
  7. Closed: want to gain knowledge and know evrything about Jaguar core.

    Started by nick123, 3rd September 2014 07:54
    • Replies: 0
    • Views: 531
    3rd September 2014, 07:54 Go to last post
  8. Closed: CPLD Help needed from a begginer

    Started by thebadtall, 31st August 2014 15:33
    • Replies: 4
    • Views: 638
    2nd September 2014, 18:43 Go to last post
  9. Closed: Nexys 3 FPGA board, communicate using USB

    Started by fahum, 2nd September 2014 13:34
    • Replies: 3
    • Views: 1,310
    2nd September 2014, 18:32 Go to last post
  10. Closed: vhdl code for spli-radix fft

    Started by nick123, 2nd September 2014 07:49
    • Replies: 1
    • Views: 603
    2nd September 2014, 07:58 Go to last post
  11. Closed: vhdl test bench problem

    Started by emanuelalkobi, 31st August 2014 11:11
    • Replies: 3
    • Views: 626
    2nd September 2014, 07:53 Go to last post
    • Replies: 0
    • Views: 603
    2nd September 2014, 05:41 Go to last post
  12. Closed: Interfacing a SRAM with Zedboard

    Started by probus, 1st September 2014 19:46
    • Replies: 0
    • Views: 597
    1st September 2014, 19:46 Go to last post
  13. Closed: pre and post shifting in floating point arithmetic

    Started by arishsu, 1st September 2014 10:39
    • Replies: 0
    • Views: 370
    1st September 2014, 10:39 Go to last post
  14. Closed: [Incisive/NCSim] Cadence Training Materials

    Started by ivlsi, 31st August 2014 22:28
    • Replies: 0
    • Views: 882
    31st August 2014, 22:28 Go to last post
    • Replies: 5
    • Views: 1,440
    31st August 2014, 21:58 Go to last post
  15. Closed: VHDL array port map assigment

    Started by shaiko, 29th August 2014 10:48
    • Replies: 17
    • Views: 1,543
    31st August 2014, 17:49 Go to last post
  16. Closed: FPGA synthesizable verilog code with floating point numbers

    Started by akipro, 31st August 2014 16:12
    • Replies: 2
    • Views: 886
    31st August 2014, 16:53 Go to last post
  17. Closed: SDRAM signals managing

    Started by Binome, 30th August 2014 11:42
    • Replies: 0
    • Views: 457
    30th August 2014, 11:42 Go to last post
  18. Closed: req: vhdl spi interface for resolver (e.g. ad2s 12-series)

    Started by nicklas_a74, 30th August 2014 10:50
    • Replies: 1
    • Views: 545
    30th August 2014, 11:20 Go to last post
  19. Closed: Unable to generate ap_idle as high in Vivado HLS

    Started by achaleus, 30th August 2014 10:45
    • Replies: 0
    • Views: 573
    30th August 2014, 10:45 Go to last post
  20. Closed: problem with test bench for a PS/2 port bidirectional tramsmit

    Started by eternalXL, 28th August 2014 01:05
    • Replies: 11
    • Views: 883
    30th August 2014, 09:26 Go to last post
  21. [SOLVED]Closed: Difference between <= Relational operator and <= Non blocking assignment

    Started by debasish_deka, 29th August 2014 06:23
    • Replies: 9
    • Views: 1,539
    29th August 2014, 22:47 Go to last post
  22. Closed: Lattice Semiconductor bitstream

    Started by campo85, 29th August 2014 08:28
    • Replies: 4
    • Views: 557
    29th August 2014, 16:39 Go to last post
  23. Closed: Question about different ways of describing MUX in Verilog

    Started by nervecell_23, 29th August 2014 16:00
    • Replies: 1
    • Views: 505
    29th August 2014, 16:27 Go to last post
  24. Closed: Have you ever used Nios with Cyclone II ?

    Started by bianchi77, 4th August 2014 12:15
    • Replies: 10
    • Views: 1,095
    27th August 2014, 22:58 Go to last post
  25. Closed: VHDL "assert" vs "report"

    Started by shaiko, 26th August 2014 21:44
    • Replies: 3
    • Views: 1,148
    27th August 2014, 12:32 Go to last post
  26. Closed: flash ram interface test bench

    Started by kranthi_vlsi, 27th August 2014 05:43
    • Replies: 1
    • Views: 492
    27th August 2014, 08:03 Go to last post
  27. Closed: [Moved]Regarding CRC in SystemVerilog

    Started by vamsanisaahith, 27th August 2014 07:51
    • Replies: 1
    • Views: 509
    27th August 2014, 08:02 Go to last post