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Threads 3001 to 3030 of 22009

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

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  1. Closed: how to connect External memory to altera fpga

    Started by zarakhan, 10th October 2014 12:14
    3 Pages
    1 2 3
    • Replies: 41
    • Views: 4,670
    14th October 2014, 08:56 Go to last post
  2. [SOLVED]Closed: compare two text files using verilog..........

    Started by dipin, 9th October 2014 12:46
    • Replies: 9
    • Views: 2,649
    14th October 2014, 08:02 Go to last post
  3. Closed: Understanding of a program in system verilog

    Started by maxxtorr723, 13th October 2014 21:36
    • Replies: 1
    • Views: 601
    13th October 2014, 23:56 Go to last post
  4. [SOLVED]Closed: Query : No display on monitor ( 800*600 resolution ) VGA CONTROLLER BASYS 2 BOARD

    Started by sukanya28, 6th October 2014 11:54
    2 Pages
    1 2
    • Replies: 26
    • Views: 2,135
    13th October 2014, 17:06 Go to last post
  5. Closed: Digital OscilloScope Working

    Started by Ashkar, 11th October 2014 11:09
    • Replies: 8
    • Views: 825
    13th October 2014, 10:13 Go to last post
  6. [SOLVED]Closed: Implementing FIFO with Cyclone 1 embedded memory

    Started by DRO, 10th October 2014 14:10
    • Replies: 9
    • Views: 602
    10th October 2014, 16:41 Go to last post
  7. Closed: matlab code for .coe file conversion into image

    Started by priyankadarkunde, 17th January 2014 11:04
    • Replies: 4
    • Views: 2,134
    10th October 2014, 11:32 Go to last post
  8. Closed: [Moved] Field programmable gate array

    Started by Vimalab, 10th October 2014 09:45
    • Replies: 1
    • Views: 489
    10th October 2014, 10:52 Go to last post
    • Replies: 2
    • Views: 841
    9th October 2014, 16:16 Go to last post
  9. Closed: online adder and signed digit vhdl code conversion problem

    Started by ghattas.akkad, 4th October 2014 13:44
    • Replies: 5
    • Views: 947
    8th October 2014, 18:25 Go to last post
  10. Closed: power consumption in circuits

    Started by ssubha, 8th October 2014 09:29
    • Replies: 1
    • Views: 385
    8th October 2014, 16:17 Go to last post
  11. Closed: vector waveform for AND gate

    Started by vead, 8th October 2014 08:24
    • Replies: 1
    • Views: 517
    8th October 2014, 12:09 Go to last post
  12. Closed: measure power consumption of sequential circuit with cache

    Started by ssubha, 8th October 2014 08:53
    • Replies: 0
    • Views: 543
    8th October 2014, 08:53 Go to last post
  13. Closed: Real time clock in verilog

    Started by santh92, 12th September 2014 05:40
    • Replies: 6
    • Views: 5,560
    7th October 2014, 17:01 Go to last post
  14. Closed: Dcm_clkgenerator multiplication in spartan-6

    Started by santh92, 7th October 2014 12:07
    • Replies: 1
    • Views: 498
    7th October 2014, 14:53 Go to last post
  15. Closed: System verilog file reading and writing

    Started by rajavel.rv, 6th October 2014 07:27
    • Replies: 2
    • Views: 997
    7th October 2014, 10:52 Go to last post
  16. Closed: PWM creator, and counter

    Started by Paul Wardlaw, 6th October 2014 14:59
    • Replies: 2
    • Views: 662
    7th October 2014, 03:18 Go to last post
  17. Closed: RS232 vhd controller

    Started by JoseL, 6th October 2014 13:03
    • Replies: 4
    • Views: 1,069
    7th October 2014, 02:57 Go to last post
  18. [SOLVED]Closed: Help needed in Booth algorithm.

    Started by gstekboy, 4th October 2014 06:13
    • Replies: 4
    • Views: 617
    6th October 2014, 18:11 Go to last post
  19. Closed: Strange behavior when reading ROM data in Altera

    Started by zermelo, 6th October 2014 15:04
    • Replies: 4
    • Views: 740
    6th October 2014, 16:58 Go to last post
  20. Closed: VHDL Synthesis Code help ,required clarification.

    Started by Y.SAI SARASWATHI, 16th September 2014 15:17
    • Replies: 8
    • Views: 886
    6th October 2014, 10:42 Go to last post
  21. Closed: verilog code for digital fir filter

    Started by MURALIMAHARAJAN, 5th October 2014 05:40
    • Replies: 1
    • Views: 1,435
    5th October 2014, 15:06 Go to last post
  22. Closed: Need help to understand simple error code VHDL

    Started by mrclrn, 4th October 2014 23:56
    • Replies: 1
    • Views: 573
    5th October 2014, 02:42 Go to last post
  23. Closed: Purpose of breakpoints in Modelsim

    Started by shaiko, 4th October 2014 09:26
    • Replies: 1
    • Views: 527
    4th October 2014, 09:35 Go to last post
  24. Closed: powerplay analyzer help

    Started by ihjay, 3rd October 2014 01:25
    • Replies: 2
    • Views: 661
    4th October 2014, 05:48 Go to last post
  25. Closed: Error in Synthesis in Xilinx ISE 14.7 (INTERNAL_ERROR)

    Started by blakes7, 2nd October 2014 04:25
    • Replies: 1
    • Views: 4,454
    2nd October 2014, 18:15 Go to last post
  26. Closed: [Moved] Implementation of PID controller in verilog.......

    Started by Vimalab, 2nd October 2014 07:20
    • Replies: 4
    • Views: 1,384
    2nd October 2014, 18:09 Go to last post
    • Replies: 2
    • Views: 960
    1st October 2014, 20:28 Go to last post
  27. Closed: meaning of spddiv speeddiv (.dividend (32'd1200...

    Started by Vimalab, 1st October 2014 13:15
    • Replies: 1
    • Views: 655
    1st October 2014, 14:55 Go to last post