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Threads 3001 to 3030 of 21964

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: tcam memory implement in sram architecture

    Started by mahalakshmi r, 26th September 2014 19:13
    • Replies: 1
    • Views: 535
    26th September 2014, 22:03 Go to last post
  2. Closed: tcam memory parity bit generation for parameter extractor

    Started by mahalakshmi r, 26th September 2014 10:38
    • Replies: 3
    • Views: 631
    26th September 2014, 21:45 Go to last post
  3. Closed: Procedural Assignment error (verilog )

    Started by vead, 23rd September 2014 06:42
    2 Pages
    1 2
    • Replies: 32
    • Views: 5,742
    26th September 2014, 18:28 Go to last post
  4. Closed: low frequency clocks generation in xilinx clock wizard

    Started by kommu4946, 12th September 2014 17:06
    • Replies: 9
    • Views: 2,185
    26th September 2014, 16:02 Go to last post
  5. Closed: [VHDL] Bus resolution function integer from multiple driver

    Started by Ronfante, 26th August 2014 13:22
    • Replies: 12
    • Views: 1,227
    26th September 2014, 15:24 Go to last post
    • Replies: 0
    • Views: 604
    26th September 2014, 07:36 Go to last post
  6. Closed: Fix error in this Verilog code

    Started by prakhars, 24th September 2014 13:16
    • Replies: 15
    • Views: 1,309
    25th September 2014, 21:30 Go to last post
    • Replies: 7
    • Views: 965
    25th September 2014, 20:01 Go to last post
  7. Closed: Differential signals as single ended connection

    Started by AWahab, 24th September 2014 13:22
    • Replies: 16
    • Views: 1,545
    25th September 2014, 14:32 Go to last post
  8. [SOLVED]Closed: Regarding : Post synthesis simulation

    Started by verylsi, 24th September 2014 09:43
    • Replies: 8
    • Views: 629
    25th September 2014, 05:18 Go to last post
  9. Closed: VHDL - Nbit multiplier test bench

    Started by S S Rayudu, 24th September 2014 17:45
    • Replies: 2
    • Views: 1,272
    24th September 2014, 21:46 Go to last post
  10. [SOLVED]Closed: checking saturation logic

    Started by rakeshk.r, 24th September 2014 10:19
    • Replies: 4
    • Views: 493
    24th September 2014, 18:56 Go to last post
  11. Closed: Verilog HDL for clock frequency divider

    Started by amerah, 24th September 2014 12:16
    • Replies: 3
    • Views: 1,691
    24th September 2014, 14:35 Go to last post
  12. Closed: migrating a design from Lattice to Altera

    Started by shaiko, 21st September 2014 18:15
    • Replies: 11
    • Views: 927
    24th September 2014, 06:36 Go to last post
  13. Closed: [Moved] How to divide any numbers in Verilog

    Started by prakhars, 23rd September 2014 09:54
    • Replies: 6
    • Views: 1,335
    24th September 2014, 04:55 Go to last post
  14. Closed: EP4CE6 and EP4CE10, same device?

    Started by Big Boy, 22nd September 2014 19:44
    • Replies: 3
    • Views: 1,305
    23rd September 2014, 19:56 Go to last post
  15. Closed: Spartan 3E LCD verilog code problem

    Started by arishsu, 11th September 2014 06:07
    • Replies: 6
    • Views: 1,707
    23rd September 2014, 16:50 Go to last post
  16. Closed: [MOVED] Code for Decimal to Binary conversion using Verilog

    Started by Sree Lahari, 22nd September 2014 11:42
    • Replies: 3
    • Views: 2,007
    23rd September 2014, 14:23 Go to last post
  17. [SOLVED]Closed: uniformly distributed random number [0,1]

    Started by rakeshk.r, 15th September 2014 17:11
    • Replies: 11
    • Views: 1,039
    23rd September 2014, 13:33 Go to last post
  18. Closed: 5:2 Compressor Block Diagram & Truth Table

    Started by sid_27, 23rd July 2014 09:39
    • Replies: 11
    • Views: 1,491
    23rd September 2014, 13:20 Go to last post
  19. Closed: problem with vhdl code

    Started by barathceg, 23rd September 2014 10:35
    • Replies: 2
    • Views: 567
    23rd September 2014, 11:12 Go to last post
  20. Closed: Need maximum voltage among two inputs

    Started by Muthuraja.M, 23rd September 2014 07:28
    • Replies: 2
    • Views: 548
    23rd September 2014, 09:45 Go to last post
  21. Closed: how to make 8 bit in verilog

    Started by vead, 22nd September 2014 15:36
    • Replies: 2
    • Views: 528
    22nd September 2014, 16:24 Go to last post
  22. Closed: Standard log2 function for integers

    Started by shaiko, 21st September 2014 23:54
    • Replies: 5
    • Views: 1,005
    22nd September 2014, 10:57 Go to last post
  23. Closed: Nexys 3 Board problem with reading /writing registers

    Started by makanaky, 20th September 2014 14:36
    • Replies: 9
    • Views: 792
    22nd September 2014, 00:07 Go to last post
  24. Closed: Accesing the properties of a component port

    Started by shaiko, 21st September 2014 11:21
    • Replies: 1
    • Views: 536
    21st September 2014, 11:59 Go to last post
  25. Closed: leaving a VHDL port open

    Started by shaiko, 21st September 2014 10:53
    • Replies: 1
    • Views: 988
    21st September 2014, 11:41 Go to last post
  26. Closed: FPGA, Power Electronics, SMPS, Control

    Started by Varun Chitransh, 18th September 2014 19:11
    • Replies: 3
    • Views: 1,020
    21st September 2014, 02:28 Go to last post
  27. [SOLVED]Closed: how can i read from memory

    Started by Mina Magdy, 20th September 2014 20:34
    • Replies: 1
    • Views: 493
    20th September 2014, 20:51 Go to last post
  28. Closed: dumping the code on FPGA kit ...

    Started by gnseeta.btech, 19th September 2014 05:41
    • Replies: 15
    • Views: 1,022
    20th September 2014, 20:14 Go to last post