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Threads 3001 to 3030 of 21843

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Shift register delay generator error

    Started by shaiko, 24th August 2014 13:51
    • Replies: 13
    • Views: 876
    25th August 2014, 11:29 Go to last post
  2. Closed: initial type of std_logic_vector

    Started by rameshrai, 21st August 2014 15:14
    • Replies: 4
    • Views: 503
    24th August 2014, 17:16 Go to last post
  3. Closed: what's wrong with my division function?

    Started by shaiko, 24th August 2014 10:22
    • Replies: 4
    • Views: 614
    24th August 2014, 14:00 Go to last post
  4. [SOLVED]Closed: How to synthesis files taken from Vivado hls

    Started by achaleus, 21st August 2014 12:36
    • Replies: 4
    • Views: 2,594
    23rd August 2014, 10:52 Go to last post
  5. Closed: error- illegal reference to net

    Started by swat123, 22nd August 2014 07:39
    • Replies: 3
    • Views: 2,364
    22nd August 2014, 17:12 Go to last post
  6. Closed: Latest version of gal22v10

    Started by kiraneee227, 21st August 2014 11:57
    • Replies: 7
    • Views: 605
    22nd August 2014, 16:38 Go to last post
  7. Closed: Error in SDK: "make: *** No rule to make target"

    Started by mahound, 22nd August 2014 16:06
    • Replies: 0
    • Views: 686
    22nd August 2014, 16:06 Go to last post
  8. Closed: Will FPGA takes real time speech signal as input?

    Started by Y.SAI SARASWATHI, 20th August 2014 16:10
    • Replies: 11
    • Views: 810
    22nd August 2014, 14:56 Go to last post
  9. Closed: Simple multi-input direction circuit

    Started by Jscheel66, 14th August 2014 15:29
    • Replies: 16
    • Views: 987
    22nd August 2014, 13:45 Go to last post
  10. Closed: Writing data from memory into a text file

    Started by Gayathrirani, 20th August 2014 07:09
    • Replies: 8
    • Views: 855
    22nd August 2014, 07:04 Go to last post
  11. Closed: verilog mod3 counter query on assign statements

    Started by strangesiva, 20th August 2014 09:28
    • Replies: 3
    • Views: 849
    21st August 2014, 21:20 Go to last post
    • Replies: 1
    • Views: 654
    21st August 2014, 18:42 Go to last post
    • Replies: 17
    • Views: 6,384
    21st August 2014, 14:13 Go to last post
  12. Closed: FFT based filter from Open Core!!

    Started by h_rafii, 20th August 2014 11:06
    • Replies: 6
    • Views: 737
    21st August 2014, 08:37 Go to last post
  13. Closed: vhdl process values of signals

    Started by bob2987, 20th August 2014 15:13
    • Replies: 5
    • Views: 524
    21st August 2014, 05:28 Go to last post
  14. Closed: verification environment in vhdl

    Started by kranthi_vlsi, 20th August 2014 13:40
    • Replies: 2
    • Views: 416
    20th August 2014, 15:19 Go to last post
  15. Closed: use of gates in cells of fpga

    Started by priyankadarkunde, 20th August 2014 11:35
    • Replies: 1
    • Views: 431
    20th August 2014, 13:15 Go to last post
    • Replies: 6
    • Views: 855
    20th August 2014, 11:32 Go to last post
  16. Closed: Image file read/write in verilog/system verilog

    Started by rockgarden333, 20th August 2014 08:06
    • Replies: 0
    • Views: 1,518
    20th August 2014, 08:06 Go to last post
    • Replies: 3
    • Views: 2,427
    20th August 2014, 06:20 Go to last post
    • Replies: 7
    • Views: 1,152
    19th August 2014, 22:20 Go to last post
  17. Closed: vhdl code for dividing two number

    Started by mina.nms, 10th August 2014 17:21
    • Replies: 3
    • Views: 818
    19th August 2014, 16:30 Go to last post
  18. [SOLVED]Closed: right shift operation in verilog

    Started by dipin, 14th August 2014 12:22
    • Replies: 6
    • Views: 1,002
    19th August 2014, 09:04 Go to last post
    • Replies: 3
    • Views: 2,827
    18th August 2014, 23:45 Go to last post
    • Replies: 1
    • Views: 2,506
    18th August 2014, 11:45 Go to last post
  19. Closed: process an input signal pulse and display results

    Started by crazy-igzp, 18th August 2014 02:30
    • Replies: 1
    • Views: 539
    18th August 2014, 08:05 Go to last post
  20. Closed: std_logic_vector and signed/ unsigned mapping

    Started by rameshrai, 17th August 2014 12:25
    • Replies: 6
    • Views: 755
    17th August 2014, 16:08 Go to last post
    • Replies: 0
    • Views: 564
    17th August 2014, 15:11 Go to last post
  21. [SOLVED]Closed: 'state is unconnected in block' verilog code error

    Started by arishsu, 17th August 2014 03:22
    • Replies: 2
    • Views: 1,582
    17th August 2014, 13:51 Go to last post
  22. Closed: modelsim and aldec active hdl

    Started by rameshrai, 16th August 2014 06:39
    • Replies: 10
    • Views: 970
    17th August 2014, 11:40 Go to last post