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Threads 3001 to 3030 of 22204

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Installation of Actel / Microsemi Libero SoC on Fedora Linux

    Started by buzzerbazooka, 18th August 2012 21:49
    • Replies: 3
    • Views: 10,337
    29th November 2014, 08:15 Go to last post
    • Replies: 3
    • Views: 1,063
    28th November 2014, 21:16 Go to last post
  2. [SOLVED]Closed: Dumping out memory addresses and its contents in a file (Xilinx Spartan 6 FPGA)

    Started by dpaul, 18th November 2014 13:22
    • Replies: 6
    • Views: 1,632
    28th November 2014, 11:32 Go to last post
  3. Closed: How to increment a value in verilog?

    Started by keerthna, 28th November 2014 09:45
    • Replies: 4
    • Views: 2,969
    28th November 2014, 10:49 Go to last post
    • Replies: 1
    • Views: 727
    28th November 2014, 09:05 Go to last post
  4. Closed: CLOCK connected to non global clock pin

    Started by axcdd, 27th November 2014 13:09
    • Replies: 4
    • Views: 713
    27th November 2014, 18:32 Go to last post
    • Replies: 3
    • Views: 607
    27th November 2014, 18:02 Go to last post
  5. Closed: padding of zeros llogic in verilog

    Started by anusha vasanta, 26th November 2014 09:52
    • Replies: 15
    • Views: 3,800
    27th November 2014, 17:40 Go to last post
  6. Closed: handshaking signals for uart

    Started by DEVI403, 24th November 2014 05:33
    • Replies: 2
    • Views: 881
    27th November 2014, 17:23 Go to last post
  7. Closed: iimplementation to FPGA

    Started by rekhavp, 26th November 2014 16:55
    • Replies: 7
    • Views: 677
    27th November 2014, 06:48 Go to last post
  8. Closed: What can cause synthesis-dependent intermittents?

    Started by Artlav, 25th November 2014 23:50
    • Replies: 5
    • Views: 886
    27th November 2014, 00:31 Go to last post
  9. Closed: Is it just me? ...............

    Started by mrflibble, 26th November 2014 11:26
    • Replies: 9
    • Views: 975
    26th November 2014, 23:12 Go to last post
  10. Closed: Refactoring revisited

    Started by mrflibble, 26th November 2014 11:16
    • Replies: 6
    • Views: 920
    26th November 2014, 20:38 Go to last post
  11. Closed: function of Adder and MUX in the given

    Started by vishal_sonam, 26th November 2014 19:47
    • Replies: 2
    • Views: 564
    26th November 2014, 20:13 Go to last post
  12. Closed: I need to learn VHDL.

    Started by vishal_sonam, 26th November 2014 08:46
    • Replies: 6
    • Views: 900
    26th November 2014, 19:21 Go to last post
  13. Closed: Canny Edge Detector in XSG

    Started by nick123, 21st November 2014 10:53
    • Replies: 3
    • Views: 1,195
    26th November 2014, 18:58 Go to last post
  14. Closed: 16x4 memory using behavioral model

    Started by Ayyappa Gollu, 22nd November 2014 20:56
    • Replies: 3
    • Views: 826
    26th November 2014, 16:34 Go to last post
  15. Closed: any one famiar with PLDA EZDMA PCIe Core?

    Started by Port Map, 26th November 2014 14:24
    • Replies: 0
    • Views: 797
    26th November 2014, 14:24 Go to last post
  16. Closed: What is an “overlapped instruction execution”?

    Started by vishal_sonam, 26th November 2014 10:21
    • Replies: 1
    • Views: 971
    26th November 2014, 10:32 Go to last post
  17. Closed: differences between for...loop and for...generate

    Started by Binome, 25th November 2014 16:50
    • Replies: 6
    • Views: 897
    26th November 2014, 08:36 Go to last post
    • Replies: 0
    • Views: 511
    26th November 2014, 07:15 Go to last post
  18. Closed: Is this a correct way to instantiate multiple modules

    Started by anusha vasanta, 25th November 2014 12:04
    • Replies: 3
    • Views: 875
    26th November 2014, 07:09 Go to last post
  19. Closed: crc 32 ethernet-magic number

    Started by Nandini Ganig, 26th November 2014 02:55
    • Replies: 0
    • Views: 1,697
    26th November 2014, 02:55 Go to last post
  20. Closed: estimated critical path coverage

    Started by abu9022, 25th November 2014 18:59
    • Replies: 2
    • Views: 758
    26th November 2014, 02:39 Go to last post
  21. Closed: doubt in VHDL testbench

    Started by abu9022, 26th November 2014 00:18
    • Replies: 1
    • Views: 735
    26th November 2014, 02:05 Go to last post
  22. [SOLVED]Closed: Constraining gated clock outputs

    Started by axcdd, 25th November 2014 09:11
    • Replies: 10
    • Views: 1,933
    25th November 2014, 21:18 Go to last post
  23. Closed: Modelsim "Coverage"

    Started by shaiko, 12th November 2014 23:55
    • Replies: 14
    • Views: 1,758
    25th November 2014, 16:35 Go to last post
  24. Closed: deserializer and fpga - how to latch data

    Started by brainiac_rus, 25th November 2014 11:16
    • Replies: 1
    • Views: 732
    25th November 2014, 16:25 Go to last post
  25. Closed: extraction of synthesizable code from given code

    Started by snehalkate, 25th November 2014 07:09
    • Replies: 2
    • Views: 639
    25th November 2014, 15:18 Go to last post
  26. [SOLVED]Closed: system verilog squareroot with out rounding....

    Started by dipin, 25th November 2014 10:09
    • Replies: 2
    • Views: 2,845
    25th November 2014, 10:45 Go to last post