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Threads 3001 to 3030 of 21730

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Help for VHDL code, wrong answer

    Started by Adnan86, 22nd July 2014 16:29
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,652
    23rd July 2014, 20:51 Go to last post
  2. Closed: What is Emulation work in Industrty?

    Started by jay496, 23rd July 2014 12:37
    • Replies: 5
    • Views: 536
    23rd July 2014, 15:48 Go to last post
  3. Closed: [Moved] what is bit- true implementation

    Started by preethi19, 22nd July 2014 05:12
    • Replies: 4
    • Views: 1,869
    23rd July 2014, 13:14 Go to last post
    • Replies: 4
    • Views: 700
    23rd July 2014, 02:04 Go to last post
  4. Closed: Mamdani Fuzzy Inference System in FPGA

    Started by nami31, 23rd July 2014 01:40
    • Replies: 0
    • Views: 500
    23rd July 2014, 01:40 Go to last post
  5. Closed: How to use Altera cyclone and VGA monitor ?

    Started by bianchi77, 22nd July 2014 23:27
    • Replies: 1
    • Views: 592
    23rd July 2014, 01:25 Go to last post
  6. Closed: Problem when simulating a register

    Started by Binome, 17th July 2014 10:21
    • Replies: 11
    • Views: 657
    22nd July 2014, 14:10 Go to last post
  7. Closed: 2D-Array Write into a file

    Started by sresam89, 17th July 2014 00:50
    • Replies: 3
    • Views: 556
    22nd July 2014, 14:09 Go to last post
  8. Closed: altera fir compiler channel manage

    Started by franticEB, 22nd July 2014 10:02
    • Replies: 3
    • Views: 593
    22nd July 2014, 14:08 Go to last post
  9. Closed: incrementing unsigned array

    Started by shaiko, 27th June 2014 15:52
    • Replies: 5
    • Views: 529
    21st July 2014, 22:50 Go to last post
  10. Closed: revolution counter for motor

    Started by kranthi_vlsi, 21st July 2014 13:52
    • Replies: 1
    • Views: 475
    21st July 2014, 18:17 Go to last post
  11. Closed: costnat value for whole matrix in VHDL

    Started by Adnan86, 20th July 2014 21:41
    • Replies: 11
    • Views: 693
    21st July 2014, 16:15 Go to last post
    • Replies: 6
    • Views: 627
    21st July 2014, 16:13 Go to last post
  12. Closed: USB device on Spartan6 evaluation board

    Started by alphus, 21st July 2014 08:32
    • Replies: 0
    • Views: 570
    21st July 2014, 08:32 Go to last post
  13. Closed: multicore leon3 with snapgear linux

    Started by Makni, 20th July 2014 22:15
    • Replies: 0
    • Views: 611
    20th July 2014, 22:15 Go to last post
  14. Closed: which board to buy altera FPGA

    Started by ghattas.akkad, 19th July 2014 19:00
    • Replies: 6
    • Views: 820
    20th July 2014, 19:40 Go to last post
  15. Closed: fpga based m.e project

    Started by mahaanjali, 16th July 2014 05:58
    • Replies: 13
    • Views: 1,013
    20th July 2014, 06:06 Go to last post
    • Replies: 3
    • Views: 634
    20th July 2014, 02:09 Go to last post
  16. Closed: BASYS2 PmodAD1 (ADC) in Verilog

    Started by blackmage, 17th July 2014 16:54
    • Replies: 3
    • Views: 1,215
    19th July 2014, 23:29 Go to last post
  17. Closed: Compatible Board for Hybrid FPGA implementation

    Started by Kharthik Pmk, 14th July 2014 07:17
    • Replies: 1
    • Views: 565
    19th July 2014, 22:32 Go to last post
  18. Closed: Syncronous FIFO - flag generation

    Started by shaiko, 30th June 2014 13:00
    6 Pages
    1 2 3 ... 6
    • Replies: 108
    • Views: 5,757
    19th July 2014, 03:21 Go to last post
  19. Closed: how to simulate more faster with modelsim?

    Started by kissmoh, 18th July 2014 05:18
    • Replies: 3
    • Views: 633
    18th July 2014, 18:13 Go to last post
  20. Closed: Two Icons for ChipScope in one Project?

    Started by SharpWeapon, 17th July 2014 14:45
    • Replies: 14
    • Views: 1,046
    18th July 2014, 18:04 Go to last post
  21. Closed: decimation factor of a three stage cic filter

    Started by lgeorge123, 12th July 2014 12:47
    • Replies: 1
    • Views: 703
    18th July 2014, 12:57 Go to last post
    • Replies: 1
    • Views: 489
    18th July 2014, 07:38 Go to last post
  22. Closed: [Moved] variable data type verilog HDL

    Started by preethi19, 18th July 2014 05:50
    • Replies: 1
    • Views: 589
    18th July 2014, 06:11 Go to last post
  23. Closed: Random number generation with normal distribution.

    Started by mrflibble, 16th July 2014 15:58
    • Replies: 12
    • Views: 883
    18th July 2014, 01:23 Go to last post
  24. [SOLVED]Closed: VERILOG (divide by zero condition)

    Started by dipin, 17th July 2014 09:14
    • Replies: 1
    • Views: 645
    17th July 2014, 15:42 Go to last post
  25. Closed: Value of data set of overcurrent relay in IEC61850 standard

    Started by varun_agr, 17th July 2014 10:00
    • Replies: 0
    • Views: 317
    17th July 2014, 10:00 Go to last post