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Threads 3001 to 3030 of 21684

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: XIlinx Microblaze first program problem

    Started by SUNBELT, 11th July 2014 17:13
    • Replies: 1
    • Views: 1,114
    11th July 2014, 22:33 Go to last post
    • Replies: 9
    • Views: 650
    11th July 2014, 22:21 Go to last post
  2. Closed: problem with division in vhdl code

    Started by velu.plg, 10th July 2014 11:29
    • Replies: 5
    • Views: 775
    11th July 2014, 13:32 Go to last post
  3. Closed: assigning a long array to a short array

    Started by shaiko, 11th July 2014 00:16
    • Replies: 7
    • Views: 997
    11th July 2014, 13:31 Go to last post
  4. Closed: vague design question

    Started by barry, 10th July 2014 16:28
    • Replies: 3
    • Views: 528
    10th July 2014, 20:41 Go to last post
    • Replies: 5
    • Views: 1,135
    10th July 2014, 18:48 Go to last post
  5. Closed: Definition of hardware implementation

    Started by Arthur Asimov Heinlein, 9th July 2014 13:31
    • Replies: 15
    • Views: 632
    10th July 2014, 17:34 Go to last post
  6. Closed: signed wired bits calculation

    Started by kissmoh, 9th July 2014 13:46
    • Replies: 3
    • Views: 646
    10th July 2014, 14:24 Go to last post
  7. Closed: Coding for Reading an image using verilog

    Started by Gohila, 9th July 2014 11:09
    • Replies: 1
    • Views: 798
    9th July 2014, 18:27 Go to last post
  8. Closed: How to execute two or more processes sequentially ?

    Started by Dijskstra, 8th July 2014 15:32
    • Replies: 7
    • Views: 766
    9th July 2014, 08:45 Go to last post
    • Replies: 4
    • Views: 1,084
    9th July 2014, 08:34 Go to last post
  9. Closed: two read a text file in vhdl

    Started by maya t, 8th July 2014 17:05
    • Replies: 1
    • Views: 575
    9th July 2014, 08:19 Go to last post
  10. Closed: about latch using nor gates

    Started by surerdra, 9th July 2014 06:59
    • Replies: 1
    • Views: 588
    9th July 2014, 08:15 Go to last post
  11. Closed: communication between adc and fpga

    Started by surerdra, 9th July 2014 06:50
    • Replies: 1
    • Views: 590
    9th July 2014, 08:04 Go to last post
  12. Closed: verilogA Help to find frequency

    Started by Sitansusekhar, 8th July 2014 13:45
    • Replies: 0
    • Views: 433
    8th July 2014, 13:45 Go to last post
  13. Closed: Signals in a process

    Started by Binome, 7th July 2014 14:43
    • Replies: 8
    • Views: 511
    8th July 2014, 10:14 Go to last post
  14. Closed: Cyclone IV + Reading from DIP Switches

    Started by flote21, 11th June 2014 12:21
    • Replies: 7
    • Views: 963
    7th July 2014, 20:35 Go to last post
  15. [SOLVED]Closed: What does WR1_LENGTH1 means in SDRAM Controller

    Started by hilal-t, 4th July 2014 09:26
    • Replies: 5
    • Views: 852
    7th July 2014, 19:52 Go to last post
  16. Closed: Lattice CPLD timing optimization

    Started by arikp, 6th July 2014 06:32
    • Replies: 2
    • Views: 628
    7th July 2014, 19:38 Go to last post
  17. Closed: Sine wave- missing samples

    Started by Careline, 2nd July 2014 10:32
    • Replies: 10
    • Views: 798
    7th July 2014, 09:44 Go to last post
  18. Closed: manual routing in fpga Editor

    Started by mesmslampanah, 7th July 2014 08:10
    • Replies: 0
    • Views: 504
    7th July 2014, 08:10 Go to last post
    • Replies: 1
    • Views: 933
    4th July 2014, 19:59 Go to last post
  19. Closed: Latch warning - Verilog code

    Started by d0lla, 4th July 2014 17:43
    • Replies: 2
    • Views: 2,066
    4th July 2014, 19:10 Go to last post
  20. Closed: Vivado & filesets

    Started by wesleytaylor, 4th July 2014 11:20
    • Replies: 1
    • Views: 1,184
    4th July 2014, 18:27 Go to last post
  21. [SOLVED]Closed: While loop usage in vhdl is giving logical error

    Started by emmagood, 4th July 2014 02:47
    • Replies: 3
    • Views: 511
    4th July 2014, 14:53 Go to last post
  22. Closed: True Dual Port RAM ALTERA writting and reading problems

    Started by DRO, 30th June 2014 10:11
    • Replies: 16
    • Views: 1,729
    4th July 2014, 10:27 Go to last post
  23. [SOLVED]Closed: Multiple Image read in testbench

    Started by kissmoh, 3rd July 2014 08:43
    • Replies: 4
    • Views: 664
    4th July 2014, 09:15 Go to last post
  24. [SOLVED]Closed: `define under the `ifdef and `elsif in verilog

    Started by imbichie, 4th July 2014 07:04
    • Replies: 2
    • Views: 1,412
    4th July 2014, 08:30 Go to last post
  25. Closed: Reg vlsi physical design

    Started by kumar781, 4th July 2014 07:45
    • Replies: 0
    • Views: 385
    4th July 2014, 07:45 Go to last post
    • Replies: 0
    • Views: 454
    3rd July 2014, 21:10 Go to last post