1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    99,525
Page 101 of 734 FirstFirst ... 51 91 99 100 101 102 103 111 151 201 601 ... LastLast
Threads 3001 to 3030 of 22001

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: [Moved] Field programmable gate array

    Started by Vimalab, 10th October 2014 09:45
    • Replies: 1
    • Views: 489
    10th October 2014, 10:52 Go to last post
    • Replies: 2
    • Views: 839
    9th October 2014, 16:16 Go to last post
  2. Closed: online adder and signed digit vhdl code conversion problem

    Started by ghattas.akkad, 4th October 2014 13:44
    • Replies: 5
    • Views: 943
    8th October 2014, 18:25 Go to last post
  3. Closed: power consumption in circuits

    Started by ssubha, 8th October 2014 09:29
    • Replies: 1
    • Views: 383
    8th October 2014, 16:17 Go to last post
  4. Closed: vector waveform for AND gate

    Started by vead, 8th October 2014 08:24
    • Replies: 1
    • Views: 513
    8th October 2014, 12:09 Go to last post
  5. Closed: measure power consumption of sequential circuit with cache

    Started by ssubha, 8th October 2014 08:53
    • Replies: 0
    • Views: 540
    8th October 2014, 08:53 Go to last post
  6. Closed: Real time clock in verilog

    Started by santh92, 12th September 2014 05:40
    • Replies: 6
    • Views: 5,535
    7th October 2014, 17:01 Go to last post
  7. Closed: Dcm_clkgenerator multiplication in spartan-6

    Started by santh92, 7th October 2014 12:07
    • Replies: 1
    • Views: 496
    7th October 2014, 14:53 Go to last post
  8. Closed: System verilog file reading and writing

    Started by rajavel.rv, 6th October 2014 07:27
    • Replies: 2
    • Views: 995
    7th October 2014, 10:52 Go to last post
  9. Closed: PWM creator, and counter

    Started by Paul Wardlaw, 6th October 2014 14:59
    • Replies: 2
    • Views: 660
    7th October 2014, 03:18 Go to last post
  10. Closed: RS232 vhd controller

    Started by JoseL, 6th October 2014 13:03
    • Replies: 4
    • Views: 1,067
    7th October 2014, 02:57 Go to last post
  11. [SOLVED]Closed: Help needed in Booth algorithm.

    Started by gstekboy, 4th October 2014 06:13
    • Replies: 4
    • Views: 614
    6th October 2014, 18:11 Go to last post
  12. Closed: Strange behavior when reading ROM data in Altera

    Started by zermelo, 6th October 2014 15:04
    • Replies: 4
    • Views: 737
    6th October 2014, 16:58 Go to last post
  13. Closed: VHDL Synthesis Code help ,required clarification.

    Started by Y.SAI SARASWATHI, 16th September 2014 15:17
    • Replies: 8
    • Views: 884
    6th October 2014, 10:42 Go to last post
  14. Closed: verilog code for digital fir filter

    Started by MURALIMAHARAJAN, 5th October 2014 05:40
    • Replies: 1
    • Views: 1,429
    5th October 2014, 15:06 Go to last post
  15. Closed: Need help to understand simple error code VHDL

    Started by mrclrn, 4th October 2014 23:56
    • Replies: 1
    • Views: 572
    5th October 2014, 02:42 Go to last post
  16. Closed: Purpose of breakpoints in Modelsim

    Started by shaiko, 4th October 2014 09:26
    • Replies: 1
    • Views: 524
    4th October 2014, 09:35 Go to last post
  17. Closed: powerplay analyzer help

    Started by ihjay, 3rd October 2014 01:25
    • Replies: 2
    • Views: 660
    4th October 2014, 05:48 Go to last post
  18. Closed: Error in Synthesis in Xilinx ISE 14.7 (INTERNAL_ERROR)

    Started by blakes7, 2nd October 2014 04:25
    • Replies: 1
    • Views: 4,437
    2nd October 2014, 18:15 Go to last post
  19. Closed: [Moved] Implementation of PID controller in verilog.......

    Started by Vimalab, 2nd October 2014 07:20
    • Replies: 4
    • Views: 1,380
    2nd October 2014, 18:09 Go to last post
    • Replies: 2
    • Views: 955
    1st October 2014, 20:28 Go to last post
  20. Closed: meaning of spddiv speeddiv (.dividend (32'd1200...

    Started by Vimalab, 1st October 2014 13:15
    • Replies: 1
    • Views: 652
    1st October 2014, 14:55 Go to last post
  21. Closed: meaning of this statement "data<=8'h44" in verilog code?

    Started by Vimalab, 1st October 2014 09:35
    • Replies: 6
    • Views: 780
    1st October 2014, 14:19 Go to last post
  22. Closed: Synthesizable Character in VHDL

    Started by Junus2012, 30th September 2014 20:20
    • Replies: 3
    • Views: 1,170
    1st October 2014, 13:00 Go to last post
  23. Closed: meaning of timescale 1ns/1ps?

    Started by Vimalab, 1st October 2014 07:10
    • Replies: 1
    • Views: 1,908
    1st October 2014, 07:41 Go to last post
  24. Closed: Using Cyclone V qsys eclipse hello world error

    Started by Strutter, 1st October 2014 02:38
    • Replies: 0
    • Views: 508
    1st October 2014, 02:38 Go to last post
  25. Closed: help: real-time applications implemented in FPGA

    Started by zilch, 28th September 2014 13:31
    • Replies: 6
    • Views: 912
    1st October 2014, 02:29 Go to last post
  26. [SOLVED]Closed: Tool to change a file from synth to simulation values

    Started by wesleytaylor, 30th September 2014 10:31
    • Replies: 5
    • Views: 528
    30th September 2014, 16:08 Go to last post
  27. [SOLVED]Closed: problem with nonblocking assignment

    Started by dipin, 26th September 2014 12:34
    • Replies: 6
    • Views: 670
    30th September 2014, 12:25 Go to last post
  28. Closed: Why Verilog $fread Only Read til 1658 Byte?

    Started by jasonkee111, 29th September 2014 04:07
    • Replies: 2
    • Views: 1,194
    30th September 2014, 10:03 Go to last post