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Threads 3001 to 3030 of 21779

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: ISim terminated in unexpected manner

    Started by SharpWeapon, 5th August 2014 16:44
    • Replies: 7
    • Views: 2,921
    6th August 2014, 01:45 Go to last post
  2. Closed: Simple Image/Video processing algorithm in FPGA

    Started by want2LearnVlsi, 31st July 2014 08:21
    • Replies: 4
    • Views: 762
    5th August 2014, 21:15 Go to last post
  3. Closed: [Moved] Access type and pointer (sorted linked List )

    Started by maturainfankam, 5th August 2014 17:23
    • Replies: 5
    • Views: 715
    5th August 2014, 19:47 Go to last post
  4. Closed: Programming for Xilinx XC7000 Series

    Started by Zag4cpld, 4th August 2014 23:18
    • Replies: 4
    • Views: 588
    5th August 2014, 18:11 Go to last post
  5. [SOLVED]Closed: -.5 representation in binary

    Started by dipin, 5th August 2014 11:01
    • Replies: 1
    • Views: 514
    5th August 2014, 12:27 Go to last post
  6. Closed: altera DE1-SoC - ARM A9 cortex

    Started by ghattas.akkad, 2nd August 2014 16:51
    • Replies: 4
    • Views: 1,894
    5th August 2014, 12:23 Go to last post
  7. Closed: FPGA and FT2232H (Sync FIFO + JTAG port)

    Started by Thoma HAUC, 5th August 2014 09:59
    • Replies: 0
    • Views: 1,143
    5th August 2014, 09:59 Go to last post
  8. Closed: VHDL function calling problem

    Started by ruwan2, 4th August 2014 17:23
    • Replies: 8
    • Views: 2,393
    5th August 2014, 00:56 Go to last post
  9. Closed: When ....else ==> red flip to green ??

    Started by bianchi77, 3rd August 2014 06:29
    • Replies: 9
    • Views: 657
    4th August 2014, 21:31 Go to last post
  10. Closed: fdip:need help for fina l year project in dip

    Started by Daksha Khatri, 3rd August 2014 17:42
    • Replies: 3
    • Views: 544
    4th August 2014, 17:20 Go to last post
  11. Closed: How to declare bidirectional bus in verilog testbench?

    Started by thaolam, 4th August 2014 05:55
    • Replies: 1
    • Views: 1,048
    4th August 2014, 15:30 Go to last post
  12. Closed: Reg Motion Estimation Papers

    Started by invlsi, 4th August 2014 13:39
    • Replies: 0
    • Views: 330
    4th August 2014, 13:39 Go to last post
  13. [SOLVED]Closed: division in FPGA using verilog

    Started by dipin, 30th July 2014 12:44
    2 Pages
    1 2
    • Replies: 20
    • Views: 4,682
    4th August 2014, 10:53 Go to last post
  14. Closed: VMEbus interface controller

    Started by Oveis.Gharan, 1st August 2014 16:49
    • Replies: 1
    • Views: 393
    4th August 2014, 05:32 Go to last post
  15. Closed: Help design a video system with multiple cameras

    Started by ahgu, 1st August 2014 19:52
    • Replies: 2
    • Views: 665
    3rd August 2014, 18:40 Go to last post
  16. Closed: Easy question about pipeline: Is this code synthesizable?

    Started by flote21, 28th July 2014 20:50
    • Replies: 8
    • Views: 705
    2nd August 2014, 17:12 Go to last post
    • Replies: 2
    • Views: 1,025
    2nd August 2014, 09:16 Go to last post
    • Replies: 3
    • Views: 1,050
    1st August 2014, 20:30 Go to last post
  17. Closed: Why Xilinx Embedded processor did not be continued?

    Started by Oveis.Gharan, 30th July 2014 08:25
    • Replies: 6
    • Views: 652
    1st August 2014, 16:37 Go to last post
  18. Closed: Error: Clock tree synthesis in Encounter 10.1

    Started by sudeep_, 31st July 2014 14:04
    • Replies: 1
    • Views: 597
    1st August 2014, 15:05 Go to last post
  19. Closed: Atlys Digilent DDR2 MIG

    Started by maxlutece, 30th July 2014 11:28
    • Replies: 9
    • Views: 1,437
    1st August 2014, 10:42 Go to last post
    • Replies: 6
    • Views: 573
    1st August 2014, 00:14 Go to last post
  20. Closed: Inferring DSP48s(four slices) as 35x35 muliplier

    Started by SharpWeapon, 30th July 2014 10:43
    • Replies: 9
    • Views: 1,097
    31st July 2014, 18:49 Go to last post
    • Replies: 2
    • Views: 548
    31st July 2014, 14:15 Go to last post
  21. Closed: Unreached status in a FSM

    Started by Dijskstra, 29th July 2014 01:14
    • Replies: 3
    • Views: 668
    31st July 2014, 10:19 Go to last post
  22. Closed: broadside and skewed test

    Started by velu.plg, 31st July 2014 08:30
    • Replies: 0
    • Views: 397
    31st July 2014, 08:30 Go to last post
  23. Closed: Help with verilog - Better way of implementing this?

    Started by vakilp, 29th July 2014 21:53
    • Replies: 3
    • Views: 765
    30th July 2014, 17:59 Go to last post
  24. Closed: Verilog beginner doubts

    Started by Raagasudha, 28th July 2014 10:18
    • Replies: 5
    • Views: 712
    30th July 2014, 15:30 Go to last post
  25. [SOLVED]Closed: fractional representation in verilog

    Started by dipin, 29th July 2014 09:35
    • Replies: 5
    • Views: 2,221
    30th July 2014, 11:24 Go to last post
  26. Closed: Quad port design from two Dual port BRAMs

    Started by SharpWeapon, 29th July 2014 11:34
    • Replies: 2
    • Views: 688
    29th July 2014, 23:45 Go to last post