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Threads 3001 to 3030 of 22100

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: convolutional encoder output xilinx

    Started by rameshrai, 2nd November 2014 12:48
    • Replies: 6
    • Views: 1,183
    6th November 2014, 14:14 Go to last post
  2. Closed: xilinx ise 9.1i simulation error

    Started by mihirengg19, 3rd November 2014 11:41
    • Replies: 9
    • Views: 2,027
    6th November 2014, 10:24 Go to last post
  3. Closed: DAC on STRATIX II EP2S60

    Started by mehanathan, 31st October 2014 10:43
    • Replies: 3
    • Views: 832
    5th November 2014, 10:30 Go to last post
  4. Closed: Strange warning in Synplify PRO

    Started by shaiko, 4th November 2014 11:02
    • Replies: 15
    • Views: 1,719
    5th November 2014, 07:50 Go to last post
  5. [SOLVED]Closed: input vector monitoring concurrent BIST architecture using S-RAM cells

    Started by selvamani, 10th October 2014 09:24
    • Replies: 1
    • Views: 856
    5th November 2014, 07:14 Go to last post
  6. Closed: Fastest method to read/write data into Nexys3 FPGA board

    Started by makanaky, 3rd November 2014 22:05
    • Replies: 3
    • Views: 1,954
    5th November 2014, 01:59 Go to last post
  7. Closed: Power calculation from synthesis report

    Started by shan14, 4th November 2014 06:28
    • Replies: 2
    • Views: 790
    4th November 2014, 09:23 Go to last post
  8. Closed: VHDL inner component with inout port

    Started by shaiko, 3rd November 2014 18:59
    • Replies: 13
    • Views: 2,154
    3rd November 2014, 22:36 Go to last post
  9. Closed: Quartus - range in generation scheme must be static

    Started by shaiko, 2nd November 2014 22:18
    • Replies: 18
    • Views: 2,342
    3rd November 2014, 20:41 Go to last post
  10. Closed: what to do "Path is unconstrained"

    Started by abu9022, 2nd November 2014 22:34
    • Replies: 4
    • Views: 2,298
    3rd November 2014, 17:58 Go to last post
  11. Closed: How to solve Hold Time Violation

    Started by abu9022, 2nd November 2014 04:32
    • Replies: 4
    • Views: 1,503
    3rd November 2014, 17:46 Go to last post
  12. Closed: Memory Conflict in Xilinx

    Started by Gayathrirani, 28th October 2014 07:12
    • Replies: 5
    • Views: 1,530
    3rd November 2014, 17:24 Go to last post
  13. Closed: Create a group of setup timing error

    Started by abu9022, 3rd November 2014 08:15
    • Replies: 2
    • Views: 683
    3rd November 2014, 10:32 Go to last post
  14. Closed: Modified booth algorithm [project help needed]

    Started by gstekboy, 2nd November 2014 09:41
    • Replies: 1
    • Views: 972
    3rd November 2014, 02:44 Go to last post
  15. [SOLVED]Closed: Parallel MAC unit design problems.[Need help]

    Started by gstekboy, 15th October 2014 07:34
    • Replies: 9
    • Views: 1,222
    2nd November 2014, 15:00 Go to last post
  16. Closed: Career guidance in VLSI having some experience

    Started by alokkmr18, 1st November 2014 14:52
    • Replies: 4
    • Views: 780
    2nd November 2014, 12:05 Go to last post
  17. Closed: Knew verilog, vhdl digital design basic.

    Started by Damomeera, 8th October 2014 23:57
    • Replies: 4
    • Views: 898
    2nd November 2014, 07:38 Go to last post
  18. Closed: Verilog RAM initialization

    Started by riky126, 1st November 2014 13:14
    • Replies: 1
    • Views: 1,661
    2nd November 2014, 06:24 Go to last post
  19. Closed: Time percentage for write mode in scrubbing

    Started by msdarvishi, 2nd November 2014 02:12
    • Replies: 1
    • Views: 472
    2nd November 2014, 02:49 Go to last post
  20. Closed: 16 bit carry look ahead adder

    Started by Mkhitar Ghazaryan, 31st October 2014 13:47
    • Replies: 2
    • Views: 2,118
    1st November 2014, 13:21 Go to last post
  21. Closed: Sine Wave Generation on an FPGA

    Started by Christian Chetcuti, 28th October 2014 08:19
    • Replies: 4
    • Views: 1,086
    31st October 2014, 17:01 Go to last post
  22. Closed: Vhdl model for single d-type latch with 3-state output

    Started by naijacoding, 31st October 2014 02:39
    • Replies: 3
    • Views: 720
    31st October 2014, 15:00 Go to last post
  23. Closed: FPGA Kit and Better HDL

    Started by pavan garate, 26th October 2014 07:09
    • Replies: 10
    • Views: 1,038
    31st October 2014, 08:49 Go to last post
  24. [SOLVED]Closed: is this a correct way to Add +neg_tchk to consider Negative Delay value

    Started by abu9022, 30th October 2014 20:51
    • Replies: 1
    • Views: 1,968
    31st October 2014, 03:21 Go to last post
  25. Closed: "whack-a-mole" game prototype using FPGA

    Started by zilch, 30th October 2014 03:13
    • Replies: 11
    • Views: 2,049
    31st October 2014, 02:15 Go to last post
  26. Closed: Limitations and Advantages with Partial Reconfiguration in FPGAs

    Started by msdarvishi, 28th October 2014 02:51
    • Replies: 1
    • Views: 660
    31st October 2014, 00:47 Go to last post
  27. Closed: Writing a verilog code for a crossbar switch

    Started by prasan61, 6th November 2011 19:58
    • Replies: 4
    • Views: 4,352
    30th October 2014, 16:35 Go to last post
  28. Closed: 8 bit sine wave to a 12 bit input dac

    Started by Christian Chetcuti, 30th October 2014 09:31
    • Replies: 2
    • Views: 652
    30th October 2014, 14:17 Go to last post
  29. Closed: preferred design for floating point comparision

    Started by seeker_123, 29th October 2014 13:34
    • Replies: 7
    • Views: 878
    30th October 2014, 14:05 Go to last post
  30. Closed: Choice of Hardware for SATA

    Started by Sunayana Chakradhar, 24th October 2014 20:55
    • Replies: 8
    • Views: 1,152
    30th October 2014, 01:36 Go to last post