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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 27,402
    25th March 2007, 08:41 Go to last post
  1. Open source Transistor level simulator

    Started by ansari haris, Yesterday 15:36
    • Replies: 2
    • Views: 133
    Today, 04:27 Go to last post
  2. set_transition_delay interpretation

    Started by kaushikrvs, Yesterday 10:06
    • Replies: 1
    • Views: 75
    Yesterday, 14:56 Go to last post
  3. [Moved] Combinational loop synthesis

    Started by kaushikrvs, 13th October 2017 10:43
    • Replies: 16
    • Views: 677
    Yesterday, 14:51 Go to last post
  4. Moved: Latch Synthesis and Precautions

    Started by kaushikrvs, Yesterday 14:13
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  5. How to use lowVT and high Vt in 45nm technology

    Started by Ash93, 14th October 2017 04:35
    • Replies: 1
    • Views: 209
    16th October 2017, 10:46 Go to last post
  6. Is there a static RTL coverage analyze tool?

    Started by eruisi, 13th October 2017 07:14
    • Replies: 3
    • Views: 238
    13th October 2017, 14:23 Go to last post
  7. Problem while using primetime

    Started by Shivani1995, 12th October 2017 15:01
    • Replies: 3
    • Views: 326
    13th October 2017, 14:22 Go to last post
  8. Different shells while using synopsis tools.

    Started by Nancy12345, 13th October 2017 07:06
    • Replies: 1
    • Views: 119
    13th October 2017, 08:41 Go to last post
  9. Synopsys dedign vision and generic (VHDL)

    Started by svip, 12th October 2017 13:05
    • Replies: 1
    • Views: 179
    12th October 2017, 14:12 Go to last post
  10. Why hold is not affected be jitter?

    Started by kaushikrvs, 10th October 2017 12:49
    • Replies: 4
    • Views: 440
    11th October 2017, 19:09 Go to last post
    • Replies: 2
    • Views: 347
    10th October 2017, 15:42 Go to last post
  11. Coupling capacitance in Digital design

    Started by kaushikrvs, 10th October 2017 11:06
    • Replies: 1
    • Views: 237
    10th October 2017, 15:14 Go to last post
  12. commit remove_clock_gates command

    Started by ua6bqg, 4th October 2017 11:39
    • Replies: 8
    • Views: 739
    9th October 2017, 19:57 Go to last post
    • Replies: 2
    • Views: 362
    9th October 2017, 14:54 Go to last post
  13. placements of pads and padring

    Started by AsharAliQureshi, 9th October 2017 07:23
    • Replies: 1
    • Views: 262
    9th October 2017, 14:49 Go to last post
    • Replies: 1
    • Views: 1,030
    29th September 2017, 20:41 Go to last post
    • Replies: 2
    • Views: 724
    29th September 2017, 17:38 Go to last post
  14. How to insert your POWER pads to your design

    Started by sanjaysharmaiitk, 22nd September 2017 07:37
    • Replies: 4
    • Views: 974
    29th September 2017, 14:27 Go to last post
  15. UART softcore testbench

    Started by promach, 7th June 2017 14:40
    • Replies: 7
    • Views: 1,036
    28th September 2017, 22:19 Go to last post
    • Replies: 4
    • Views: 617
    28th September 2017, 14:49 Go to last post
  16. enable vs reset in digital IC

    Started by carmeloA, 17th September 2017 21:04
    • Replies: 17
    • Views: 1,185
    27th September 2017, 22:48 Go to last post
    • Replies: 0
    • Views: 434
    27th September 2017, 06:08 Go to last post
  17. how to wire testbench for "INPUT" pin in verilg

    Started by sanjaysharmaiitk, 26th September 2017 08:18
    • Replies: 1
    • Views: 386
    26th September 2017, 13:54 Go to last post
  18. Frequency division:unusual ratios

    Started by Peppew, 19th September 2017 15:53
    • Replies: 1
    • Views: 696
    19th September 2017, 16:04 Go to last post
  19. Measure Bandwith with T-spice

    Started by rafauy, 15th September 2017 21:08
    • Replies: 1
    • Views: 554
    18th September 2017, 19:46 Go to last post
  20. How to identify driver and loads of a net from SPEF file

    Started by ttxs, 12th September 2017 00:50
    • Replies: 7
    • Views: 904
    18th September 2017, 19:45 Go to last post
  21. Tcl script for DRC of Standard Cells

    Started by Johannah, 18th September 2017 07:27
    • Replies: 2
    • Views: 516
    18th September 2017, 16:49 Go to last post