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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 27,500
    25th March 2007, 08:41 Go to last post
  1. Multicycle path and metastability

    Started by stanford, 20th October 2017 00:45
    • Replies: 8
    • Views: 357
    Yesterday, 23:43 Go to last post
  2. How to use lowVT and high Vt in 45nm technology

    Started by Ash93, 14th October 2017 04:35
    • Replies: 3
    • Views: 365
    Yesterday, 22:09 Go to last post
  3. [Moved] Combinational loop synthesis

    Started by kaushikrvs, 13th October 2017 10:43
    • Replies: 17
    • Views: 939
    20th October 2017, 08:41 Go to last post
  4. Current design in prime time

    Started by Shivani1995, 18th October 2017 16:43
    • Replies: 1
    • Views: 184
    19th October 2017, 14:43 Go to last post
  5. [SOLVED] Request for a basic verification code example in Verilog

    Started by bit_an, 18th October 2017 10:11
    • Replies: 3
    • Views: 316
    18th October 2017, 18:45 Go to last post
  6. Open source Transistor level simulator

    Started by ansari haris, 17th October 2017 15:36
    • Replies: 2
    • Views: 245
    18th October 2017, 04:27 Go to last post
  7. set_transition_delay interpretation

    Started by kaushikrvs, 17th October 2017 10:06
    • Replies: 1
    • Views: 165
    17th October 2017, 14:56 Go to last post
  8. Moved: Latch Synthesis and Precautions

    Started by kaushikrvs, 17th October 2017 14:13
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  9. Is there a static RTL coverage analyze tool?

    Started by eruisi, 13th October 2017 07:14
    • Replies: 3
    • Views: 332
    13th October 2017, 14:23 Go to last post
  10. Problem while using primetime

    Started by Shivani1995, 12th October 2017 15:01
    • Replies: 3
    • Views: 408
    13th October 2017, 14:22 Go to last post
  11. Different shells while using synopsis tools.

    Started by Nancy12345, 13th October 2017 07:06
    • Replies: 1
    • Views: 190
    13th October 2017, 08:41 Go to last post
  12. Synopsys dedign vision and generic (VHDL)

    Started by svip, 12th October 2017 13:05
    • Replies: 1
    • Views: 250
    12th October 2017, 14:12 Go to last post
  13. Why hold is not affected be jitter?

    Started by kaushikrvs, 10th October 2017 12:49
    • Replies: 4
    • Views: 523
    11th October 2017, 19:09 Go to last post
    • Replies: 2
    • Views: 416
    10th October 2017, 15:42 Go to last post
  14. Coupling capacitance in Digital design

    Started by kaushikrvs, 10th October 2017 11:06
    • Replies: 1
    • Views: 311
    10th October 2017, 15:14 Go to last post
  15. commit remove_clock_gates command

    Started by ua6bqg, 4th October 2017 11:39
    • Replies: 8
    • Views: 805
    9th October 2017, 19:57 Go to last post
    • Replies: 2
    • Views: 430
    9th October 2017, 14:54 Go to last post
  16. placements of pads and padring

    Started by AsharAliQureshi, 9th October 2017 07:23
    • Replies: 1
    • Views: 328
    9th October 2017, 14:49 Go to last post
    • Replies: 1
    • Views: 1,094
    29th September 2017, 20:41 Go to last post
    • Replies: 2
    • Views: 794
    29th September 2017, 17:38 Go to last post
  17. How to insert your POWER pads to your design

    Started by sanjaysharmaiitk, 22nd September 2017 07:37
    • Replies: 4
    • Views: 1,040
    29th September 2017, 14:27 Go to last post
  18. UART softcore testbench

    Started by promach, 7th June 2017 14:40
    • Replies: 7
    • Views: 1,109
    28th September 2017, 22:19 Go to last post
    • Replies: 4
    • Views: 684
    28th September 2017, 14:49 Go to last post
  19. enable vs reset in digital IC

    Started by carmeloA, 17th September 2017 21:04
    • Replies: 17
    • Views: 1,262
    27th September 2017, 22:48 Go to last post
    • Replies: 0
    • Views: 500
    27th September 2017, 06:08 Go to last post