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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 28,211
    25th March 2007, 08:41 Go to last post
  1. VHDL code for phase matching

    Started by ananthan95, 3rd November 2017 13:21
    • Replies: 13
    • Views: 2,731
    Yesterday, 19:01 Go to last post
    • Replies: 15
    • Views: 1,564
    20th November 2017, 22:15 Go to last post
  2. Question on dc_topographical script ??

    Started by hcu, 4th November 2017 09:04
    • Replies: 1
    • Views: 788
    17th November 2017, 15:36 Go to last post
  3. XAUI (10G) Combo Port PHY for Ehternet Switch

    Started by Rahul Soni, 14th November 2017 08:32
    • Replies: 1
    • Views: 1,374
    14th November 2017, 15:33 Go to last post
  4. How to decide memory extra margin adjustment (EMA)

    Started by superpanda, 14th November 2017 03:12
    • Replies: 3
    • Views: 594
    14th November 2017, 15:31 Go to last post
  5. How to highlight systemverilog syntax

    Started by jdshah, 13th November 2017 13:29
    • Replies: 2
    • Views: 590
    13th November 2017, 17:20 Go to last post
    • Replies: 3
    • Views: 1,262
    12th November 2017, 21:20 Go to last post
  6. Variable clock generation in verilog using task

    Started by raghavkmr, 20th January 2015 06:57
    • Replies: 4
    • Views: 2,679
    10th November 2017, 17:19 Go to last post
  7. Get TLUPLUS from ICT/capTable ?

    Started by GDesign, 10th November 2017 10:28
    • Replies: 1
    • Views: 477
    10th November 2017, 17:17 Go to last post
  8. Lvt cells along critical path

    Started by Ash93, 2nd November 2017 01:26
    • Replies: 9
    • Views: 1,907
    9th November 2017, 15:06 Go to last post
  9. Sequential Circuit Timing Analysis

    Started by farabi2017, 2nd November 2017 17:06
    • Replies: 7
    • Views: 993
    8th November 2017, 21:39 Go to last post
  10. Current design in prime time

    Started by Shivani1995, 18th October 2017 16:43
    • Replies: 10
    • Views: 1,184
    7th November 2017, 17:06 Go to last post
    • Replies: 1
    • Views: 1,561
    7th November 2017, 10:21 Go to last post
    • Replies: 1
    • Views: 1,203
    6th November 2017, 09:49 Go to last post
  11. Simple questions about synchronizer

    Started by promach, 4th November 2017 08:36
    • Replies: 0
    • Views: 431
    4th November 2017, 08:36 Go to last post
    • Replies: 5
    • Views: 1,078
    3rd November 2017, 20:54 Go to last post
  12. Single Stage Logic gate meaning

    Started by Arokia, 28th October 2017 17:10
    • Replies: 6
    • Views: 1,514
    30th October 2017, 19:35 Go to last post
    • Replies: 1
    • Views: 627
    30th October 2017, 15:54 Go to last post
    • Replies: 1
    • Views: 591
    30th October 2017, 15:41 Go to last post
    • Replies: 4
    • Views: 829
    30th October 2017, 15:12 Go to last post
    • Replies: 1
    • Views: 605
    27th October 2017, 21:30 Go to last post
  13. Simulation guideline of RTL and Netlist mixed simulation

    Started by mchengh, 27th October 2017 13:11
    • Replies: 5
    • Views: 675
    27th October 2017, 20:35 Go to last post
    • Replies: 2
    • Views: 602
    27th October 2017, 20:29 Go to last post
  14. What happens if we give 5v to a 2v standard cell ?

    Started by kaushikrvs, 27th October 2017 07:50
    • Replies: 2
    • Views: 575
    27th October 2017, 16:13 Go to last post
  15. set_skew_group with icg cells

    Started by ua6bqg, 27th October 2017 15:11
    • Replies: 0
    • Views: 525
    27th October 2017, 15:11 Go to last post
    • Replies: 1
    • Views: 542
    27th October 2017, 14:32 Go to last post
    • Replies: 1
    • Views: 591
    26th October 2017, 11:17 Go to last post