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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 24,717
    25th March 2007, 08:41 Go to last post
  1. GP vs LP standard cell libraries

    Started by oAwad, Today 07:31
    • Replies: 1
    • Views: 145
    Today, 14:37 Go to last post
  2. Cadence SoC encounter IN LINUX

    Started by DocIng, 7th December 2016 15:54
    • Replies: 9
    • Views: 1,225
    Today, 14:03 Go to last post
  3. clock tree synthesis

    Started by oAwad, Today 11:47
    • Replies: 0
    • Views: 84
    Today, 11:47 Go to last post
  4. Cordic Algorithm Question

    Started by promach, 13th May 2017 07:45
    • Replies: 19
    • Views: 2,158
    Yesterday, 15:54 Go to last post
  5. Implication of not specifying input delay constraint

    Started by mwb, 18th May 2017 19:04
    • Replies: 4
    • Views: 447
    18th May 2017, 20:35 Go to last post
  6. DRC Violations in Encounter

    Started by inputoutput, 12th May 2017 16:51
    • Replies: 7
    • Views: 518
    18th May 2017, 19:07 Go to last post
  7. Unsynthesizable verilog code

    Started by Johannah, 15th May 2017 04:17
    • Replies: 7
    • Views: 494
    17th May 2017, 09:58 Go to last post
  8. Automatic routing in SoC Encounter

    Started by oAwad, 16th May 2017 22:13
    • Replies: 0
    • Views: 249
    16th May 2017, 22:13 Go to last post
  9. clock tree sysnthesis

    Started by atlaakreddy, 15th May 2017 07:30
    • Replies: 6
    • Views: 359
    16th May 2017, 14:25 Go to last post
  10. Component Declaration in VHDL

    Started by dzafar, 16th May 2017 09:47
    • Replies: 1
    • Views: 212
    16th May 2017, 09:56 Go to last post
    • Replies: 2
    • Views: 253
    15th May 2017, 18:57 Go to last post
  11. full chip power analysis in HSIM

    Started by oAwad, 15th May 2017 12:47
    • Replies: 3
    • Views: 161
    15th May 2017, 13:31 Go to last post
  12. what is antenna violation? wen it will pccur?

    Started by atlaakreddy, 12th May 2017 13:04
    • Replies: 3
    • Views: 259
    15th May 2017, 13:21 Go to last post
    • Replies: 3
    • Views: 446
    14th May 2017, 20:55 Go to last post
  13. looking for ultra low threshold 45nm spice model

    Started by oAwad, 14th May 2017 11:40
    • Replies: 1
    • Views: 236
    14th May 2017, 19:42 Go to last post
    • Replies: 0
    • Views: 134
    13th May 2017, 15:34 Go to last post
  14. transistor model in SPICE simulation

    Started by oAwad, 11th May 2017 12:42
    • Replies: 6
    • Views: 594
    13th May 2017, 04:33 Go to last post
    • Replies: 1
    • Views: 169
    12th May 2017, 16:48 Go to last post
    • Replies: 2
    • Views: 204
    12th May 2017, 15:54 Go to last post
  15. [SOLVED] Place and Route in SoC Encounter

    Started by oAwad, 11th May 2017 09:01
    • Replies: 2
    • Views: 273
    11th May 2017, 15:56 Go to last post
  16. tempus STA - internal library pins in SDC

    Started by slakshmi, 8th May 2017 17:11
    • Replies: 6
    • Views: 948
    10th May 2017, 13:35 Go to last post
  17. Floor Plan Row Spacing

    Started by inputoutput, 8th May 2017 18:50
    • Replies: 4
    • Views: 503
    9th May 2017, 04:35 Go to last post
  18. Encounter Timing System

    Started by J.J.Reddy, 6th May 2017 06:56
    • Replies: 1
    • Views: 507
    6th May 2017, 16:03 Go to last post
  19. Use of pdk info in layout

    Started by sandeeprev, 6th May 2017 12:14
    • Replies: 1
    • Views: 244
    6th May 2017, 16:02 Go to last post
  20. Low-Power design with Innovus using UPF

    Started by diogorsousa, 2nd May 2017 10:58
    • Replies: 4
    • Views: 815
    4th May 2017, 14:34 Go to last post
  21. HSPICE error for CNTFET simulation

    Started by kkvepa, 3rd May 2017 23:25
    • Replies: 0
    • Views: 366
    3rd May 2017, 23:25 Go to last post