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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 25,294
    25th March 2007, 08:41 Go to last post
  1. Macro delay in clock tree synthesis

    Started by oAwad, Yesterday 18:00
    • Replies: 1
    • Views: 328
    Today, 02:24 Go to last post
    • Replies: 4
    • Views: 264
    Yesterday, 20:50 Go to last post
  2. how to fix setup and hold on same path

    Started by mepriyasingh, 1st November 2016 19:21
    • Replies: 11
    • Views: 899
    Yesterday, 17:23 Go to last post
    • Replies: 5
    • Views: 460
    Yesterday, 08:31 Go to last post
  3. Standard cell placement in SoC Encounter

    Started by oAwad, 23rd June 2017 17:33
    • Replies: 1
    • Views: 107
    23rd June 2017, 17:41 Go to last post
  4. Fractional clock divider

    Started by promach, 23rd June 2017 16:04
    • Replies: 1
    • Views: 104
    23rd June 2017, 16:18 Go to last post
    • Replies: 3
    • Views: 144
    21st June 2017, 17:20 Go to last post
    • Replies: 1
    • Views: 289
    19th June 2017, 16:35 Go to last post
    • Replies: 2
    • Views: 468
    19th June 2017, 07:43 Go to last post
  5. fan-out 4 inveter(fo4)

    Started by hamedtz, 18th June 2017 10:13
    • Replies: 1
    • Views: 416
    18th June 2017, 17:49 Go to last post
    • Replies: 2
    • Views: 412
    17th June 2017, 05:32 Go to last post
  6. Worst negative slack increases during post-CTS

    Started by inputoutput, 15th June 2017 12:40
    • Replies: 3
    • Views: 757
    15th June 2017, 20:59 Go to last post
  7. Inserting clk delay not clk buffer

    Started by bit_an, 15th June 2017 08:51
    • Replies: 4
    • Views: 352
    15th June 2017, 16:02 Go to last post
  8. Formality Verification Failed: RTL vs netlist

    Started by Johannah, 15th June 2017 03:00
    • Replies: 2
    • Views: 299
    15th June 2017, 15:57 Go to last post
  9. Connecting 2D array output to 1D array input

    Started by bit_an, 14th June 2017 10:52
    • Replies: 3
    • Views: 255
    14th June 2017, 17:41 Go to last post
  10. Need a detailed notes on tsmc library files

    Started by hcu, 12th June 2017 07:34
    • Replies: 7
    • Views: 909
    14th June 2017, 15:37 Go to last post
  11. [SOLVED] Understanding the STIL file after ATPG

    Started by aditmohan96, 13th June 2017 15:24
    • Replies: 0
    • Views: 216
    13th June 2017, 15:24 Go to last post
  12. Calculating spacing between metal5 stripes

    Started by kannanunni, 8th June 2017 07:27
    • Replies: 3
    • Views: 571
    12th June 2017, 14:24 Go to last post
  13. Power optimization commands in design compiler

    Started by inputoutput, 10th June 2017 17:36
    • Replies: 1
    • Views: 539
    12th June 2017, 14:22 Go to last post
  14. tempus STA - internal library pins in SDC

    Started by slakshmi, 8th May 2017 17:11
    • Replies: 8
    • Views: 1,494
    12th June 2017, 14:21 Go to last post
  15. Constraints in a design

    Started by DocIng, 5th June 2017 22:57
    • Replies: 6
    • Views: 656
    10th June 2017, 15:08 Go to last post
    • Replies: 1
    • Views: 668
    9th June 2017, 08:35 Go to last post
  16. Ungrouping breaks ECO flow

    Started by englishdogg, 7th June 2017 05:55
    • Replies: 4
    • Views: 547
    9th June 2017, 07:45 Go to last post
  17. [SOLVED] Meaning of 'Macro depth'

    Started by circuit.maker, 6th June 2017 10:01
    • Replies: 3
    • Views: 423
    9th June 2017, 00:47 Go to last post
  18. Timing and power analysis of a digital layout

    Started by oAwad, 8th June 2017 16:06
    • Replies: 1
    • Views: 272
    9th June 2017, 00:46 Go to last post
  19. Voltus power analysis of a macro

    Started by kenambo, 6th June 2017 12:58
    • Replies: 5
    • Views: 531
    8th June 2017, 14:56 Go to last post