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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 24,799
    25th March 2007, 08:41 Go to last post
  1. Cordic Algorithm Question

    Started by promach, 13th May 2017 07:45
    2 Pages
    1 2
    • Replies: 26
    • Views: 2,872
    Yesterday, 19:04 Go to last post
  2. introduce delay in a gate clock in SoC Encounter

    Started by oAwad, 26th May 2017 12:50
    • Replies: 3
    • Views: 806
    Yesterday, 14:41 Go to last post
  3. IC LED Driver, Low Current

    Started by Chips & Chips, 24th May 2017 07:34
    • Replies: 3
    • Views: 412
    26th May 2017, 09:13 Go to last post
  4. Cadence SoC encounter IN LINUX

    Started by DocIng, 7th December 2016 15:54
    • Replies: 13
    • Views: 1,648
    26th May 2017, 08:59 Go to last post
  5. Metastable signal ANDed with logic 0

    Started by Ashish Agrawal, 25th May 2017 07:35
    • Replies: 1
    • Views: 107
    25th May 2017, 15:36 Go to last post
  6. what if metastability settles to a wrong value

    Started by twainerm, 25th May 2017 06:15
    • Replies: 2
    • Views: 210
    25th May 2017, 08:31 Go to last post
  7. Need help with this code

    Started by haneet, 24th May 2017 23:27
    • Replies: 1
    • Views: 201
    25th May 2017, 02:19 Go to last post
  8. Implication of not specifying input delay constraint

    Started by mwb, 18th May 2017 19:04
    • Replies: 8
    • Views: 659
    24th May 2017, 19:28 Go to last post
  9. clock tree sysnthesis

    Started by atlaakreddy, 15th May 2017 07:30
    • Replies: 7
    • Views: 461
    24th May 2017, 16:02 Go to last post
  10. transistor ageing in chip

    Started by shweta.bphc, 24th May 2017 02:09
    • Replies: 3
    • Views: 203
    24th May 2017, 04:56 Go to last post
  11. GP vs LP standard cell libraries

    Started by oAwad, 23rd May 2017 07:31
    • Replies: 1
    • Views: 234
    23rd May 2017, 14:37 Go to last post
  12. clock tree synthesis

    Started by oAwad, 23rd May 2017 11:47
    • Replies: 0
    • Views: 165
    23rd May 2017, 11:47 Go to last post
  13. DRC Violations in Encounter

    Started by inputoutput, 12th May 2017 16:51
    • Replies: 7
    • Views: 565
    18th May 2017, 19:07 Go to last post
  14. Unsynthesizable verilog code

    Started by Johannah, 15th May 2017 04:17
    • Replies: 7
    • Views: 544
    17th May 2017, 09:58 Go to last post
  15. Automatic routing in SoC Encounter

    Started by oAwad, 16th May 2017 22:13
    • Replies: 0
    • Views: 287
    16th May 2017, 22:13 Go to last post
  16. Component Declaration in VHDL

    Started by dzafar, 16th May 2017 09:47
    • Replies: 1
    • Views: 255
    16th May 2017, 09:56 Go to last post
    • Replies: 2
    • Views: 293
    15th May 2017, 18:57 Go to last post
  17. full chip power analysis in HSIM

    Started by oAwad, 15th May 2017 12:47
    • Replies: 3
    • Views: 207
    15th May 2017, 13:31 Go to last post
  18. what is antenna violation? wen it will pccur?

    Started by atlaakreddy, 12th May 2017 13:04
    • Replies: 3
    • Views: 298
    15th May 2017, 13:21 Go to last post
    • Replies: 3
    • Views: 491
    14th May 2017, 20:55 Go to last post
  19. looking for ultra low threshold 45nm spice model

    Started by oAwad, 14th May 2017 11:40
    • Replies: 1
    • Views: 275
    14th May 2017, 19:42 Go to last post
    • Replies: 0
    • Views: 168
    13th May 2017, 15:34 Go to last post
  20. transistor model in SPICE simulation

    Started by oAwad, 11th May 2017 12:42
    • Replies: 6
    • Views: 636
    13th May 2017, 04:33 Go to last post
    • Replies: 1
    • Views: 201
    12th May 2017, 16:48 Go to last post
    • Replies: 2
    • Views: 244
    12th May 2017, 15:54 Go to last post
  21. [SOLVED] Place and Route in SoC Encounter

    Started by oAwad, 11th May 2017 09:01
    • Replies: 2
    • Views: 315
    11th May 2017, 15:56 Go to last post
  22. tempus STA - internal library pins in SDC

    Started by slakshmi, 8th May 2017 17:11
    • Replies: 6
    • Views: 995
    10th May 2017, 13:35 Go to last post
  23. Floor Plan Row Spacing

    Started by inputoutput, 8th May 2017 18:50
    • Replies: 4
    • Views: 542
    9th May 2017, 04:35 Go to last post