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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 26,975
    25th March 2007, 08:41 Go to last post
  1. How to insert your POWER pads to your design

    Started by sanjaysharmaiitk, 22nd September 2017 07:37
    • Replies: 1
    • Views: 385
    Yesterday, 00:46 Go to last post
  2. Frequency division:unusual ratios

    Started by Peppew, 19th September 2017 15:53
    • Replies: 1
    • Views: 374
    19th September 2017, 16:04 Go to last post
    • Replies: 0
    • Views: 276
    18th September 2017, 19:49 Go to last post
  3. Measure Bandwith with T-spice

    Started by rafauy, 15th September 2017 21:08
    • Replies: 1
    • Views: 257
    18th September 2017, 19:46 Go to last post
  4. How to identify driver and loads of a net from SPEF file

    Started by ttxs, 12th September 2017 00:50
    • Replies: 7
    • Views: 566
    18th September 2017, 19:45 Go to last post
  5. enable vs reset in digital IC

    Started by carmeloA, 17th September 2017 21:04
    • Replies: 8
    • Views: 398
    18th September 2017, 18:02 Go to last post
  6. Tcl script for DRC of Standard Cells

    Started by Johannah, 18th September 2017 07:27
    • Replies: 2
    • Views: 198
    18th September 2017, 16:49 Go to last post
  7. Unresolved cells in Design compiler

    Started by sh.j, 4th September 2017 06:07
    • Replies: 1
    • Views: 410
    16th September 2017, 14:58 Go to last post
  8. Formal verification with don't touch cell

    Started by Johannah, 5th September 2017 08:35
    • Replies: 2
    • Views: 432
    16th September 2017, 14:56 Go to last post
    • Replies: 2
    • Views: 331
    16th September 2017, 14:52 Go to last post
  9. synthesis question about generated clocks

    Started by sitawman, 4th September 2017 03:30
    • Replies: 4
    • Views: 493
    15th September 2017, 16:00 Go to last post
  10. Pipeline Distributed arithmetic design

    Started by sumbal.ali, 13th September 2017 10:50
    • Replies: 1
    • Views: 346
    13th September 2017, 16:47 Go to last post
  11. How to add extra hold time slack?

    Started by sitawman, 11th September 2017 03:16
    • Replies: 9
    • Views: 591
    13th September 2017, 02:28 Go to last post
    • Replies: 0
    • Views: 403
    9th September 2017, 17:11 Go to last post
  12. using modelsim with tsmc 0.18u library

    Started by tanish, 6th September 2017 08:23
    • Replies: 8
    • Views: 654
    7th September 2017, 22:17 Go to last post
  13. VDD and ground pins in IC compiler

    Started by sitawman, 7th September 2017 07:48
    • Replies: 1
    • Views: 298
    7th September 2017, 19:18 Go to last post
  14. layout versus schematic verification

    Started by atlaakreddy, 2nd September 2017 15:36
    • Replies: 9
    • Views: 599
    6th September 2017, 09:21 Go to last post
  15. congestion after postRoute

    Started by bangcy, 2nd September 2017 21:43
    • Replies: 5
    • Views: 668
    5th September 2017, 15:45 Go to last post
  16. store data in registers to control mode of ic

    Started by sanjaysharmaiitk, 4th September 2017 14:50
    • Replies: 1
    • Views: 333
    4th September 2017, 16:03 Go to last post
  17. acceptable voltage drop for power line 1V?

    Started by hamed_Golden, 3rd September 2017 05:45
    • Replies: 2
    • Views: 435
    3rd September 2017, 23:04 Go to last post
  18. antenna rule checks in the physical verification

    Started by atlaakreddy, 2nd September 2017 15:19
    • Replies: 0
    • Views: 333
    2nd September 2017, 15:19 Go to last post
  19. Always-on power domain voltage

    Started by vcnvcc, 25th August 2017 12:00
    • Replies: 4
    • Views: 678
    2nd September 2017, 08:22 Go to last post
  20. MIX Vt cells in clock tree

    Started by GDesign, 1st September 2017 11:31
    • Replies: 2
    • Views: 470
    1st September 2017, 15:20 Go to last post
  21. How to merge 2 LEF designs in Synopsys IC Compiler II?

    Started by majd229, 29th August 2017 22:13
    • Replies: 11
    • Views: 768
    31st August 2017, 15:11 Go to last post
    • Replies: 6
    • Views: 831
    31st August 2017, 14:26 Go to last post
  22. si double switching violations

    Started by cyrax747, 30th August 2017 05:20
    • Replies: 1
    • Views: 469
    30th August 2017, 14:41 Go to last post
  23. synthesys in synopsys design compiler

    Started by abhishek7, 19th August 2017 06:07
    • Replies: 3
    • Views: 1,028
    29th August 2017, 09:13 Go to last post
  24. [SOLVED] unequal transition time for the pins connected to one net

    Started by ua6bqg, 3rd August 2017 10:54
    • Replies: 10
    • Views: 1,581
    29th August 2017, 09:09 Go to last post
  25. Placement in innovus (encouner) cad tool

    Started by sanjaysharmaiitk, 26th August 2017 16:09
    • Replies: 3
    • Views: 740
    28th August 2017, 14:27 Go to last post
    • Replies: 1
    • Views: 630
    25th August 2017, 01:27 Go to last post