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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 26,344
    25th March 2007, 08:41 Go to last post
  1. difference between cdl and sp file.

    Started by sanjaysharmaiitk, 17th August 2017 11:33
    • Replies: 3
    • Views: 599
    Yesterday, 14:22 Go to last post
    • Replies: 1
    • Views: 104
    Yesterday, 14:21 Go to last post
  2. synthesys in synopsys design compiler

    Started by abhishek7, 19th August 2017 06:07
    • Replies: 2
    • Views: 481
    Yesterday, 14:19 Go to last post
    • Replies: 1
    • Views: 283
    21st August 2017, 16:21 Go to last post
  3. ECSM characterization

    Started by viviadam, 16th August 2017 07:23
    • Replies: 0
    • Views: 401
    16th August 2017, 07:23 Go to last post
  4. What's the CCOpt replacement for bufferTreeSynthesis?

    Started by digitalo, 10th August 2017 12:59
    • Replies: 4
    • Views: 574
    14th August 2017, 14:24 Go to last post
  5. The EDA design tool for GaAs substrate.

    Started by hg81, 12th August 2017 04:16
    • Replies: 3
    • Views: 449
    12th August 2017, 18:57 Go to last post
  6. VLAN tag. When it is take out?

    Started by julian403, 30th July 2017 20:30
    • Replies: 4
    • Views: 609
    12th August 2017, 09:27 Go to last post
    • Replies: 6
    • Views: 461
    12th August 2017, 00:57 Go to last post
  7. [SOLVED] [moved] VCS option for linking a library during runtime for DPI

    Started by nivedhis, 1st August 2017 01:25
    • Replies: 1
    • Views: 470
    10th August 2017, 19:06 Go to last post
  8. [Moved]: saed-90nm library files

    Started by jmaileh.b, 10th August 2017 07:57
    • Replies: 1
    • Views: 272
    10th August 2017, 15:36 Go to last post
  9. Moved: [Moved]Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
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    • Replies: 1
    • Views: 411
    9th August 2017, 16:24 Go to last post
  10. Bit blasted and bussed Netlist

    Started by a2vlsi, 8th August 2017 19:22
    • Replies: 1
    • Views: 509
    8th August 2017, 20:23 Go to last post
    • Replies: 1
    • Views: 335
    8th August 2017, 14:31 Go to last post
  11. [SOLVED] Uncomplete RC network

    Started by brunope, 3rd August 2017 13:46
    • Replies: 16
    • Views: 1,356
    8th August 2017, 07:13 Go to last post
    • Replies: 8
    • Views: 965
    5th August 2017, 16:09 Go to last post
  12. [SOLVED] 0.35um technology file for tanner v.13

    Started by shashi106, 5th August 2017 11:32
    • Replies: 1
    • Views: 384
    5th August 2017, 14:55 Go to last post
    • Replies: 7
    • Views: 929
    5th August 2017, 03:22 Go to last post
  13. Compile-time forces (NCSIM and VCS)

    Started by ads2017, 2nd August 2017 10:52
    • Replies: 9
    • Views: 611
    3rd August 2017, 14:15 Go to last post
  14. ELC Output Library Timing Resolution

    Started by Hassan14, 3rd August 2017 01:21
    • Replies: 0
    • Views: 390
    3rd August 2017, 01:21 Go to last post
  15. Conditional CDC : Timing and CDC violations

    Started by smatty, 2nd August 2017 22:40
    • Replies: 0
    • Views: 414
    2nd August 2017, 22:40 Go to last post
  16. Modelsim - Different istance of the same unit

    Started by carmeloA, 31st July 2017 11:27
    • Replies: 4
    • Views: 594
    1st August 2017, 06:47 Go to last post
  17. how to use SRAM 28nmHPC lib im my design?

    Started by abhishek7, 31st July 2017 07:51
    • Replies: 1
    • Views: 343
    31st July 2017, 18:11 Go to last post
    • Replies: 1
    • Views: 460
    30th July 2017, 17:14 Go to last post
    • Replies: 8
    • Views: 1,024
    28th July 2017, 15:24 Go to last post
    • Replies: 1
    • Views: 514
    28th July 2017, 14:06 Go to last post