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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 25,719
    25th March 2007, 08:41 Go to last post
  1. Combining two async resets

    Started by Ashish Agrawal, Yesterday 07:57
    • Replies: 6
    • Views: 366
    Today, 05:40 Go to last post
  2. Cadence Encounter LEF POLYGON error

    Started by mcaduser, Yesterday 20:46
    • Replies: 3
    • Views: 102
    Yesterday, 23:13 Go to last post
  3. carbon nano tube in pass transistor desgining

    Started by amir68, 19th July 2017 19:11
    • Replies: 6
    • Views: 277
    Yesterday, 20:10 Go to last post
  4. Floating Signal in Multi voltage design or low power

    Started by a2vlsi, 17th July 2017 21:14
    • Replies: 5
    • Views: 529
    19th July 2017, 18:38 Go to last post
  5. asynchronus to synchronous

    Started by Johannah, 19th July 2017 07:37
    • Replies: 4
    • Views: 238
    19th July 2017, 16:48 Go to last post
  6. Difference between .def and .ddc files

    Started by Muralidar_Reddy521, 5th July 2017 06:02
    • Replies: 2
    • Views: 380
    19th July 2017, 01:30 Go to last post
    • Replies: 5
    • Views: 831
    18th July 2017, 23:53 Go to last post
  7. Fix setup requirement - Innovus/Tempus

    Started by rodrigoluizb, 18th July 2017 13:39
    • Replies: 3
    • Views: 169
    18th July 2017, 18:47 Go to last post
    • Replies: 1
    • Views: 206
    18th July 2017, 14:55 Go to last post
    • Replies: 1
    • Views: 175
    17th July 2017, 19:50 Go to last post
    • Replies: 6
    • Views: 689
    17th July 2017, 16:24 Go to last post
  8. Query Related to Slack in synthesis

    Started by Daya123, 16th July 2017 08:15
    • Replies: 1
    • Views: 440
    16th July 2017, 20:40 Go to last post
  9. [Moved]: Logical Efforts - Please help

    Started by sherline123, 16th July 2017 09:55
    • Replies: 1
    • Views: 290
    16th July 2017, 20:22 Go to last post
  10. Design Compiler (Vision)

    Started by amol_elec, 10th July 2017 15:06
    • Replies: 5
    • Views: 887
    15th July 2017, 16:26 Go to last post
  11. Minimum Area with Cadence Encounter

    Started by mcaduser, 15th July 2017 03:54
    • Replies: 1
    • Views: 300
    15th July 2017, 16:25 Go to last post
  12. Voltus power analysis of a macro

    Started by kenambo, 6th June 2017 12:58
    • Replies: 7
    • Views: 1,271
    13th July 2017, 14:25 Go to last post
  13. SDF PATHPULSE construct via write_sdf command?

    Started by IADanilov, 12th July 2017 12:49
    • Replies: 1
    • Views: 310
    12th July 2017, 18:52 Go to last post
  14. Map my module to a specific standard cell

    Started by ASICTiger, 6th July 2017 22:16
    • Replies: 12
    • Views: 1,431
    11th July 2017, 00:25 Go to last post
  15. Could anyone explain about Sensitivity in SSTA

    Started by evesjh77, 10th July 2017 01:44
    • Replies: 2
    • Views: 346
    10th July 2017, 22:17 Go to last post
  16. interconnect scaling

    Started by oAwad, 8th July 2017 14:18
    • Replies: 2
    • Views: 305
    10th July 2017, 15:50 Go to last post
  17. how to create fsdb file in synopsys tools

    Started by jmaileh.b, 8th July 2017 17:43
    • Replies: 0
    • Views: 337
    8th July 2017, 17:43 Go to last post
  18. negative WNS for clock gating path

    Started by ua6bqg, 6th July 2017 12:54
    • Replies: 5
    • Views: 526
    7th July 2017, 14:16 Go to last post
  19. Synthesizing a signal as DFF and not DFFS

    Started by oAwad, 26th June 2017 08:52
    • Replies: 4
    • Views: 850
    6th July 2017, 04:26 Go to last post
    • Replies: 4
    • Views: 711
    5th July 2017, 15:22 Go to last post
  20. clock Design vs ckSynthesis

    Started by jason.wei, 5th July 2017 09:38
    • Replies: 1
    • Views: 304
    5th July 2017, 14:43 Go to last post
  21. Python Exception caught:No module named pcell

    Started by kasti, 5th July 2017 11:50
    • Replies: 1
    • Views: 248
    5th July 2017, 14:42 Go to last post
  22. Inserting clk delay not clk buffer

    Started by bit_an, 15th June 2017 08:51
    • Replies: 5
    • Views: 669
    5th July 2017, 09:13 Go to last post
    • Replies: 3
    • Views: 977
    28th June 2017, 00:44 Go to last post