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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 25,338
    25th March 2007, 08:41 Go to last post
    • Replies: 3
    • Views: 274
    Today, 00:44 Go to last post
  1. scan chain clock waveform

    Started by ua6bqg, Yesterday 12:28
    • Replies: 6
    • Views: 138
    Yesterday, 17:55 Go to last post
  2. Tool used to design SoC in ASIC flow ?

    Started by hcu, 26th June 2017 19:15
    • Replies: 3
    • Views: 395
    26th June 2017, 23:40 Go to last post
    • Replies: 9
    • Views: 603
    26th June 2017, 19:23 Go to last post
    • Replies: 4
    • Views: 236
    26th June 2017, 16:14 Go to last post
  3. Synthesizing a signal as DFF and not DFFS

    Started by oAwad, 26th June 2017 08:52
    • Replies: 1
    • Views: 102
    26th June 2017, 14:35 Go to last post
  4. Macro delay in clock tree synthesis

    Started by oAwad, 24th June 2017 18:00
    • Replies: 3
    • Views: 583
    26th June 2017, 14:30 Go to last post
    • Replies: 4
    • Views: 303
    24th June 2017, 20:50 Go to last post
  5. how to fix setup and hold on same path

    Started by mepriyasingh, 1st November 2016 19:21
    • Replies: 11
    • Views: 935
    24th June 2017, 17:23 Go to last post
  6. Standard cell placement in SoC Encounter

    Started by oAwad, 23rd June 2017 17:33
    • Replies: 1
    • Views: 145
    23rd June 2017, 17:41 Go to last post
  7. Fractional clock divider

    Started by promach, 23rd June 2017 16:04
    • Replies: 1
    • Views: 129
    23rd June 2017, 16:18 Go to last post
    • Replies: 3
    • Views: 174
    21st June 2017, 17:20 Go to last post
    • Replies: 1
    • Views: 313
    19th June 2017, 16:35 Go to last post
    • Replies: 2
    • Views: 494
    19th June 2017, 07:43 Go to last post
  8. fan-out 4 inveter(fo4)

    Started by hamedtz, 18th June 2017 10:13
    • Replies: 1
    • Views: 444
    18th June 2017, 17:49 Go to last post
    • Replies: 2
    • Views: 435
    17th June 2017, 05:32 Go to last post
  9. Worst negative slack increases during post-CTS

    Started by inputoutput, 15th June 2017 12:40
    • Replies: 3
    • Views: 786
    15th June 2017, 20:59 Go to last post
  10. Inserting clk delay not clk buffer

    Started by bit_an, 15th June 2017 08:51
    • Replies: 4
    • Views: 372
    15th June 2017, 16:02 Go to last post
  11. Formality Verification Failed: RTL vs netlist

    Started by Johannah, 15th June 2017 03:00
    • Replies: 2
    • Views: 324
    15th June 2017, 15:57 Go to last post
  12. Connecting 2D array output to 1D array input

    Started by bit_an, 14th June 2017 10:52
    • Replies: 3
    • Views: 278
    14th June 2017, 17:41 Go to last post
  13. Need a detailed notes on tsmc library files

    Started by hcu, 12th June 2017 07:34
    • Replies: 7
    • Views: 943
    14th June 2017, 15:37 Go to last post
  14. [SOLVED] Understanding the STIL file after ATPG

    Started by aditmohan96, 13th June 2017 15:24
    • Replies: 0
    • Views: 240
    13th June 2017, 15:24 Go to last post
  15. Calculating spacing between metal5 stripes

    Started by kannanunni, 8th June 2017 07:27
    • Replies: 3
    • Views: 600
    12th June 2017, 14:24 Go to last post
  16. Power optimization commands in design compiler

    Started by inputoutput, 10th June 2017 17:36
    • Replies: 1
    • Views: 563
    12th June 2017, 14:22 Go to last post
  17. tempus STA - internal library pins in SDC

    Started by slakshmi, 8th May 2017 17:11
    • Replies: 8
    • Views: 1,521
    12th June 2017, 14:21 Go to last post
  18. Constraints in a design

    Started by DocIng, 5th June 2017 22:57
    • Replies: 6
    • Views: 687
    10th June 2017, 15:08 Go to last post
    • Replies: 1
    • Views: 690
    9th June 2017, 08:35 Go to last post