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Analog IC Design & Layout
Analog IC design & Layout questions. Analog ASIC design. Semiconductor Technology issues.
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0 klug 732 03 Dec 2007 19:00
klug
No new posts CT SD ADC
7 safwatonline 186 01 May 2008 15:45
re007972
No new posts BJT ESD failure, anyone has experience with that?
10 cmosbjt 713 25 Apr 2008 4:46
elantra
No new posts about step change in the output of SC circuits
6 hr_rezaee 782 13 Feb 2008 13:14
safwatonline
No new posts How can I download the class video from standford Univ ?
1 wireless man 18 12 May 2008 23:08
js0p
No new posts Who does IC layout?
3 whiplash 12 12 May 2008 23:05
js0p
No new posts Substrate charge pump
0 js0p 6 12 May 2008 23:01
js0p
No new posts Duty cycle control of the clock
0 taofeng 12 12 May 2008 21:27
taofeng
No new posts on chip clock generator from 100KHz- 100MHz
0 taofeng 15 12 May 2008 21:23
taofeng
No new posts how to implement the addition/subtraction of two voltages
5 Octago 48 12 May 2008 18:52
Octago
No new posts Third order PLL
1 mouzid 33 12 May 2008 18:16
SergeyBondarev
No new posts Differential difference amplifier for voltages addtition?
2 Octago 36 12 May 2008 17:10
Octago
No new posts berkeley webcast video ee240 is so blurry, for help!
1 wireless man 42 12 May 2008 16:30
freelancer
No new posts Interview Question: Charge pump Gain
0 mouzid 27 12 May 2008 14:44
mouzid
No new posts what is hot topics in analog design research?
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69 bobchentan 2397 12 May 2008 14:31
The Joy of Electronics
No new posts PLL in depth
0 AdvaRes 18 12 May 2008 14:23
AdvaRes
No new posts Which OPAMP topology for Switched Cap Filter
2 shady205 21 12 May 2008 10:26
shady205
No new posts LNA post layout
1 bcdeepak 12 12 May 2008 10:09
jecyhale
No new posts Are il and ile file relative with SKILL?
3 flyankh 360 12 May 2008 4:57
soer8
No new posts capacitance
0 safwatonline 12 11 May 2008 20:05
safwatonline
No new posts Why an OTA can drive Switched-Cap circuit
1 OMEsystem 30 11 May 2008 19:46
LvW
No new posts Régulateurs
0 maahtdk 27 11 May 2008 16:28
maahtdk
No new posts Berkeley EECS140,240,247 Classes
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64 Puppet1 7773 11 May 2008 1:02
jilinhai2002
No new posts analog design and Hspice learning
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33 analog_design 3390 11 May 2008 0:38
jilinhai2002
No new posts How to simulate the loopwidth of PLL?
5 icsoul 87 11 May 2008 0:34
rfsystem
No new posts why we use 1:1, 2:1, 4:1 and 8:1 devices for BJT matching?
5 gksivas 90 10 May 2008 23:48
rfsystem
No new posts IPTAT^2 current source
3 unit900 57 10 May 2008 23:33
rfsystem
No new posts offset of fully differential amplifier
6 manissri 54 10 May 2008 18:29
kwkam
No new posts tail transistor considerations
0 spring1860 27 10 May 2008 17:06
spring1860
No new posts Subthreshold current in DTMOS transistors
0 s_babayan 21 10 May 2008 15:20
s_babayan
No new posts MOSTransistor Mismatch / Yield Analysis
7 raduga_in 777 10 May 2008 14:51
mida2621
No new posts Stability analysis for multiple fedback loops
3 drabos 51 10 May 2008 13:26
LvW
No new posts The fabrication fee of BiCMOS and CMOS process
0 chang830 24 10 May 2008 8:06
chang830
No new posts Mosfet Mismatch
6 midgariano 81 10 May 2008 6:29
dabing
No new posts about assura lvs?
2 bocinverson 96 10 May 2008 4:54
bocinverson
No new posts div-3 divider with 50 percent duty cycle?
7 bill_sun 84 10 May 2008 3:58
bill_sun
No new posts Substrate charge pump basic cell design
0 js0p 30 10 May 2008 1:28
js0p
No new posts Transistor sizing
5 AdvaRes 105 09 May 2008 21:16
drabos
No new posts RHHP and complex pole
13 ee484 168 09 May 2008 18:39
ee484
No new posts Analog and Digital Design
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75 lsp 3576 09 May 2008 17:38
rosaeidi
No new posts Jitter simulation of Oscillator using HSPICE
1 Rad_31 39 09 May 2008 15:41
Hughes
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