| Topics |
Replies |
Author |
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Last Post |
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Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!
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0 |
klug |
732 |
03 Dec 2007 19:00 klug |
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CT SD ADC
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7 |
safwatonline |
186 |
01 May 2008 15:45 re007972 |
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BJT ESD failure, anyone has experience with that?
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10 |
cmosbjt |
713 |
25 Apr 2008 4:46 elantra |
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about step change in the output of SC circuits
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6 |
hr_rezaee |
782 |
13 Feb 2008 13:14 safwatonline |
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How can I download the class video from standford Univ ?
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1 |
wireless man |
18 |
12 May 2008 23:08 js0p |
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Who does IC layout?
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3 |
whiplash |
12 |
12 May 2008 23:05 js0p |
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Substrate charge pump
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0 |
js0p |
6 |
12 May 2008 23:01 js0p |
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Duty cycle control of the clock
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0 |
taofeng |
12 |
12 May 2008 21:27 taofeng |
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on chip clock generator from 100KHz- 100MHz
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0 |
taofeng |
15 |
12 May 2008 21:23 taofeng |
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how to implement the addition/subtraction of two voltages
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5 |
Octago |
48 |
12 May 2008 18:52 Octago |
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Third order PLL
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1 |
mouzid |
33 |
12 May 2008 18:16 SergeyBondarev |
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Differential difference amplifier for voltages addtition?
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2 |
Octago |
36 |
12 May 2008 17:10 Octago |
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berkeley webcast video ee240 is so blurry, for help!
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1 |
wireless man |
42 |
12 May 2008 16:30 freelancer |
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Interview Question: Charge pump Gain
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0 |
mouzid |
27 |
12 May 2008 14:44 mouzid |
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what is hot topics in analog design research?
[ Goto page: 1, 2, 3 ] |
69 |
bobchentan |
2397 |
12 May 2008 14:31 The Joy of Electronics |
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PLL in depth
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0 |
AdvaRes |
18 |
12 May 2008 14:23 AdvaRes |
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Which OPAMP topology for Switched Cap Filter
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2 |
shady205 |
21 |
12 May 2008 10:26 shady205 |
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LNA post layout
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1 |
bcdeepak |
12 |
12 May 2008 10:09 jecyhale |
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Are il and ile file relative with SKILL?
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3 |
flyankh |
360 |
12 May 2008 4:57 soer8 |
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capacitance
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0 |
safwatonline |
12 |
11 May 2008 20:05 safwatonline |
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Why an OTA can drive Switched-Cap circuit
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1 |
OMEsystem |
30 |
11 May 2008 19:46 LvW |
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Régulateurs
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0 |
maahtdk |
27 |
11 May 2008 16:28 maahtdk |
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Berkeley EECS140,240,247 Classes
[ Goto page: 1, 2, 3 ] |
64 |
Puppet1 |
7773 |
11 May 2008 1:02 jilinhai2002 |
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analog design and Hspice learning
[ Goto page: 1, 2 ] |
33 |
analog_design |
3390 |
11 May 2008 0:38 jilinhai2002 |
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How to simulate the loopwidth of PLL?
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5 |
icsoul |
87 |
11 May 2008 0:34 rfsystem |
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why we use 1:1, 2:1, 4:1 and 8:1 devices for BJT matching?
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5 |
gksivas |
90 |
10 May 2008 23:48 rfsystem |
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IPTAT^2 current source
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3 |
unit900 |
57 |
10 May 2008 23:33 rfsystem |
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offset of fully differential amplifier
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6 |
manissri |
54 |
10 May 2008 18:29 kwkam |
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tail transistor considerations
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0 |
spring1860 |
27 |
10 May 2008 17:06 spring1860 |
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Subthreshold current in DTMOS transistors
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0 |
s_babayan |
21 |
10 May 2008 15:20 s_babayan |
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MOSTransistor Mismatch / Yield Analysis
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7 |
raduga_in |
777 |
10 May 2008 14:51 mida2621 |
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Stability analysis for multiple fedback loops
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3 |
drabos |
51 |
10 May 2008 13:26 LvW |
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The fabrication fee of BiCMOS and CMOS process
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0 |
chang830 |
24 |
10 May 2008 8:06 chang830 |
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Mosfet Mismatch
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6 |
midgariano |
81 |
10 May 2008 6:29 dabing |
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about assura lvs?
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2 |
bocinverson |
96 |
10 May 2008 4:54 bocinverson |
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div-3 divider with 50 percent duty cycle?
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7 |
bill_sun |
84 |
10 May 2008 3:58 bill_sun |
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Substrate charge pump basic cell design
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0 |
js0p |
30 |
10 May 2008 1:28 js0p |
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Transistor sizing
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5 |
AdvaRes |
105 |
09 May 2008 21:16 drabos |
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RHHP and complex pole
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13 |
ee484 |
168 |
09 May 2008 18:39 ee484 |
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Analog and Digital Design
[ Goto page: 1, 2, 3 ] |
75 |
lsp |
3576 |
09 May 2008 17:38 rosaeidi |
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Jitter simulation of Oscillator using HSPICE
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1 |
Rad_31 |
39 |
09 May 2008 15:41 Hughes |