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Analog IC Design & Layout


Analog IC design & Layout questions. Analog ASIC design. Semiconductor Technology issues.

tags: analog integrated circuits design, cmos analog design, ic analog design, circuit design, cmos design, cmos, analog layout, analog vlsi, analog voltage, op amp design, analogue, capacitor design,
Moderators: pranam77, Super Moderators

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This topic is locked: you cannot edit posts or make replies. Announcement: Read this before posting
 0 klug 2964 03 Dec 2007 18:00
klug
No new posts Analog Design Synthesis and optimization tools
 1 hock 375 30 Oct 2009 14:09
jimjim2k
No new posts Layout problem - common centroid techniques
 1 Monady 66 07 Nov 2009 14:03
erikl
No new posts what determine the supply voltage of a cmos ic chip?
 3 catrat 78 07 Nov 2009 12:56
erikl
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 4 dtzounakos 63 07 Nov 2009 1:12
dtzounakos
No new posts 1db compression point and IIp3
 2 seantan85 21 07 Nov 2009 0:03
flatulent
No new posts elementary questions about analog layout
 1 pathto_teraze 93 06 Nov 2009 20:28
erikl
No new posts SAR ADC Modeling using MATLAB
 1 fenix1 57 06 Nov 2009 17:59
JoannesPaulus
No new posts free samples of gds required
 3 cool_ic 126 06 Nov 2009 15:49
erikl
No new posts what's the difference between 3 bits slicer and 3 bits ADC?
 2 cqmyg5 183 06 Nov 2009 15:38
erikl
No new posts Masters level project in analog design
 1 Amninder 63 06 Nov 2009 11:44
saad
No new posts Updating layout
 1 pinifrancesco 63 06 Nov 2009 8:07
cop02ia
No new posts Silvaco atlas software
 1 krushiunte 48 06 Nov 2009 5:43
krushiunte
No new posts GENERAL QUESTIONS about Bandgap Reference
 3 aredhel_vlsi 123 05 Nov 2009 21:51
dick_freebird
No new posts Negitive Voltage Switch for MMIC
 0 b4bb4ge 24 05 Nov 2009 18:19
b4bb4ge
No new posts intrinsic gain of mos. Help Pleeeease.
 11 arunkumar446 639 05 Nov 2009 17:11
y7wu
No new posts What are the white spot in the die photo?
 1 fxxjssc 78 05 Nov 2009 16:26
dick_freebird
No new posts Regarding Virtuoso XL Layout Editor
 5 findsriharsha 102 05 Nov 2009 15:45
Mr.dal
No new posts how to convert current mode contro of buck converter
 0 dholevt 21 05 Nov 2009 15:09
dholevt
No new posts If you need help with ESD... ask me in this post
 14 ESDSolutions 898 05 Nov 2009 10:22
ESDSolutions
No new posts current mirror mismatch with different multiplier
 4 alex.ang1983 269 05 Nov 2009 9:49
Bahrouch
No new posts MOM capacitor problems for ADC
 1 heshufeng 36 04 Nov 2009 19:43
timof
No new posts Can we create an npn BJT in the layout instead of using one?
 4 aredhel_vlsi 168 04 Nov 2009 19:15
aredhel_vlsi
No new posts NBTI simulation tutorial using ELDO
 1 dyan83 15 04 Nov 2009 17:30
erikl
No new posts port names in pex.netlist is Upper Case !
 0 bsrin 21 04 Nov 2009 15:31
bsrin
No new posts opamp design - bias current of 10uA Vsupply=3.3v.
 3 ramya19 135 04 Nov 2009 13:32
pianomania
No new posts why does NMOS pass a strong logic 0 and a weak logic 1
 12 Shanthanayaki 1610 04 Nov 2009 12:45
suze
No new posts Offset of folding signals
 2 kickbeer 72 04 Nov 2009 11:14
kickbeer
No new posts Assura LVS warning shortened internal nets
 1 varunmjman 33 04 Nov 2009 5:17
deepak242003
No new posts Native device layout problem
 5 santhua 378 04 Nov 2009 4:18
evi
No new posts MATLAB program for SFDR!
 6 jeniffer 3183 04 Nov 2009 2:34
euniceliu
No new posts How to insert a power-cut cell?
 0 cheat0821 69 03 Nov 2009 8:23
cheat0821
No new posts Power consumption of analog DLL.
 2 JuliaJ 54 02 Nov 2009 22:42
JuliaJ
No new posts Does anyone know the symbol Er(SiO2) of 130nm proccess?
 3 dtzounakos 87 02 Nov 2009 21:48
dick_freebird
No new posts Virtuoso Analog Enviroment - Outputs Setup Problem
 2 dtzounakos 114 02 Nov 2009 16:33
dtzounakos
No new posts accurate way for calculation of oscillation frequency
 6 mohammadpiano 171 02 Nov 2009 13:47
oermens
No new posts temprature stability of bandgap design
 7 godspeed.w 249 02 Nov 2009 10:18
jesseyu1984918
No new posts cmos amp design: input is close to ground
 2 freewing 117 02 Nov 2009 10:10
jesseyu1984918
No new posts Take a look at the circuit(BGR)
 5 liuguojia387 177 02 Nov 2009 10:08
mikersia
No new posts Extracting power nets only from layout
 3 Pat_Mustard 123 02 Nov 2009 8:28
llbaobao
No new posts Question on noise_table function in verilogA?
 3 neoflash 81 02 Nov 2009 3:56
mengcy
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