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PLD, SPLD, GAL, CPLD, FPGA Design Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions. Moderator: Super Moderators		Goto page 1, 2, 3 ... 193, 194, 195  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!	0	klug	2109	21 Mar 2007 22:21 klug
	Announcement: Verilog versus VHDL	0	FORUM_RULES	8761	23 Nov 2004 20:50 FORUM_RULES
	Simulation with VHDL: How to create stimulus with Jitter?	3	Black Jack	213	23 Jul 2008 8:36 Black Jack
	Free Seminar on "Quest for Scalable Verification"	0	cvc_training	21	23 Jul 2008 6:55 cvc_training
	Free Seminar on Advanced Verification with Aldec’s Riviera	0	cvc_training	141	18 Jul 2008 8:10 cvc_training
	Convert IF-THEN-ELSE statements to the STATE MACHINE	2	BlackOps	195	15 Jul 2008 11:32 BlackOps
	Can i use Matlab(Simulink)as data source to FPGAVirtexII pro	5	m_3aziz	279	13 Jul 2008 11:21 salma ali bakr
	USB Hi-Speed data tranfer rate	4	simce	345	18 Jun 2008 14:37 voho
	Fast-Track course on Verification Using SystemVerilog @ BLR	2	aji_vlsi	312	08 Jun 2008 12:40 aji_vlsi
	Help needed on VHDL code.	14	kokei74	132	25 Jul 2008 14:16 Black Jack
	synchronous reset (verilog)	7	pwq1999	78	25 Jul 2008 14:02 pwq1999
	Delay Concept	3	dinesh.4126	45	25 Jul 2008 11:06 saikat
	anyone have Synopsis sw	0	dinesh_radaur	6	25 Jul 2008 10:38 dinesh_radaur
	block memory access prob (ISE & qu(at)rtus)	0	childs	15	25 Jul 2008 9:11 childs
	diff.b/w AES n IDEA algo.	0	gurucharan	9	25 Jul 2008 7:40 gurucharan
	ebook	1	wajahat	36	25 Jul 2008 6:15 research_vlsi
	plz help	5	zai3our	129	25 Jul 2008 5:54 khamitkar.ravikant
	urgent!! program failed in ISE 10.1	2	childs	75	25 Jul 2008 3:54 childs
	Digital Circuit Design Book Recommendation	3	cafukarfoo	120	24 Jul 2008 16:10 xihushui
	inductance and capcitor???	2	khamitkar.ravikant	78	24 Jul 2008 14:23 Davood Amerion
	microblaze	3	ck_nandy	69	24 Jul 2008 14:07 saikat
	VHDL code for serial in serial out	3	j hemangini	66	24 Jul 2008 12:07 j hemangini
	Dont understand the meaning of this LOOP (VHDL)	0	BlackOps	39	24 Jul 2008 11:17 BlackOps
	vhdl code for serial communication	12	j hemangini	111	24 Jul 2008 11:10 j hemangini
	Need code for generating clock doubler using DCM... [ Goto page: 1, 2, 3 ]	77	vidyaredy	1518	24 Jul 2008 10:56 echo47
	Electric VLSI design system by static	0	bbgil	12	24 Jul 2008 8:56 bbgil
	readmemh-reg	0	vinodkumar	27	24 Jul 2008 7:56 vinodkumar
	some more basic que......!!	1	jigisha	66	24 Jul 2008 7:13 khamitkar.ravikant
	gud evng	11	swati vsh	189	24 Jul 2008 7:12 swati vsh
	Generate initial delay after the device is programmed.	3	param	45	23 Jul 2008 12:00 param
	safe state machine problem	1	skycanny	33	23 Jul 2008 10:48 FvM
	Spartan 3AN usb data cable install problem	2	krivan	45	23 Jul 2008 9:23 krivan
	VHDL code for LCD display	3	j hemangini	84	23 Jul 2008 7:45 mehrzad321
	FPGA Selection - Xilinx or @ltera	1	nag123	42	23 Jul 2008 6:52 saikat
	understand module level utilization report in ISE 10.1	5	saikat	66	22 Jul 2008 13:29 saikat
	Floor-Planning in ISE	4	salma ali bakr	69	22 Jul 2008 12:50 salma ali bakr
	How to know if clock is toggling?	9	suquid29	162	22 Jul 2008 12:06 mehrzad321
	Urgent need for MT28F128J3 VHDL/ Verilog Contorller Please H	0	mehrzad321	27	22 Jul 2008 11:28 mehrzad321
	PLB IPIF Master Interface (VHDL templates and example soft)	0	BlackOps	18	22 Jul 2008 10:40 BlackOps
	circuit to Convert 16 bit to 8 bit	5	heythem2008	150	22 Jul 2008 7:09 Zerox100
	system generator?	5	braveprasanna	111	22 Jul 2008 5:49 khamitkar.ravikant
	A good book for Verilog programming	7	RedAlert	378	22 Jul 2008 4:58 www.testbench.in

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