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Threads 21421 to 21450 of 21841

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: NIOS and opencore ethmac?

    Started by catrat, 17th October 2003 09:35
    • Replies: 1
    • Views: 2,918
    4th November 2003, 03:22 Go to last post
  2. Closed: What generic connectors can be used with Rocket I/O?

    Started by it_boy, 27th October 2003 10:20
    • Replies: 5
    • Views: 2,363
    4th November 2003, 03:18 Go to last post
  3. Closed: few pin count but more gate array and FF stage

    Started by bunalmis, 2nd November 2003 16:52
    • Replies: 1
    • Views: 1,230
    3rd November 2003, 20:57 Go to last post
  4. Closed: how can I make the power cost lower?

    Started by mrhfw, 1st November 2003 23:43
    • Replies: 2
    • Views: 1,151
    3rd November 2003, 20:52 Go to last post
  5. Closed: Convertion of designs from Quartus to ISE

    Started by twinsen, 2nd November 2003 18:28
    • Replies: 1
    • Views: 1,414
    3rd November 2003, 00:08 Go to last post
  6. Closed: Help me with controlling 3 DC Motors using a GAL

    Started by goosiegoo, 1st November 2003 18:06
    • Replies: 1
    • Views: 1,885
    2nd November 2003, 07:12 Go to last post
  7. Closed: Video Scaler/Deinterlacer

    Started by lucbra, 30th October 2003 21:57
    • Replies: 0
    • Views: 2,035
    30th October 2003, 21:57 Go to last post
  8. Closed: FPGA Design tools: Plan*Ahead from H.i.e.r*Design

    Started by TurboPC, 30th October 2003 06:27
    • Replies: 0
    • Views: 914
    30th October 2003, 06:27 Go to last post
  9. Closed: Can you do LCD driver with a keypad using CPLD?

    Started by ZeleC, 23rd October 2003 18:40
    • Replies: 3
    • Views: 3,324
    28th October 2003, 16:47 Go to last post
  10. Closed: Modelsim - how to reset flip-flops ?

    Started by CADDevil, 28th October 2003 00:52
    • Replies: 3
    • Views: 2,389
    28th October 2003, 02:45 Go to last post
  11. Closed: link to download FPGA advantage 5.3b demo version

    Started by nega, 26th October 2003 17:04
    • Replies: 0
    • Views: 1,276
    26th October 2003, 17:04 Go to last post
  12. Closed: What is the format of hexdecimal in NCSIM TEXTIO package?

    Started by john5888, 26th October 2003 16:57
    • Replies: 0
    • Views: 895
    26th October 2003, 16:57 Go to last post
  13. Closed: SN74C926 built with GAL/PAL

    Started by killex, 25th October 2003 21:50
    • Replies: 7
    • Views: 3,919
    26th October 2003, 15:06 Go to last post
  14. Closed: external clock distribution.

    Started by elcielo, 18th September 2003 05:32
    • Replies: 4
    • Views: 1,072
    25th October 2003, 12:28 Go to last post
  15. Closed: Opinions on using code|lab for Altera NIOS

    Started by lsa1961, 23rd October 2003 10:58
    • Replies: 0
    • Views: 1,332
    23rd October 2003, 10:58 Go to last post
  16. Closed: PCI Board With Xilinx Virtex/Virtex II devices?

    Started by xfpgas, 8th October 2003 05:03
    • Replies: 4
    • Views: 3,165
    23rd October 2003, 08:27 Go to last post
  17. Closed: HELP:Can you upload some Synplify trianing han LAB materials

    Started by handsome, 22nd October 2003 03:51
    • Replies: 1
    • Views: 1,625
    22nd October 2003, 04:30 Go to last post
  18. Closed: lattice MA5 with view logic

    Started by brutus, 20th October 2003 21:39
    • Replies: 1
    • Views: 1,071
    22nd October 2003, 04:19 Go to last post
  19. Closed: How to copy a protected PAL, GAL and CPLD

    Started by weeyndha, 19th October 2003 15:44
    • Replies: 3
    • Views: 3,808
    21st October 2003, 19:10 Go to last post
  20. Closed: coding style for verilog and vhdl

    Started by rohit_tech, 16th October 2003 13:24
    • Replies: 2
    • Views: 1,787
    21st October 2003, 02:35 Go to last post
  21. Closed: Prescaler - What is going on?

    Started by Mercury, 20th October 2003 20:55
    • Replies: 2
    • Views: 4,527
    21st October 2003, 01:04 Go to last post
  22. Closed: QDR SRAM Memmory Controller

    Started by mami_hacky, 18th October 2003 07:17
    • Replies: 1
    • Views: 1,664
    20th October 2003, 22:49 Go to last post
  23. Closed: small IP core in altera cpld?

    Started by 7rots51, 19th October 2003 18:18
    • Replies: 1
    • Views: 1,862
    19th October 2003, 19:45 Go to last post
  24. Closed: Why all phases of clock placement operate on GCR in ISE 6.1?

    Started by zcq, 19th October 2003 12:21
    • Replies: 1
    • Views: 1,188
    19th October 2003, 13:24 Go to last post
  25. Closed: VHDL circuit for detecting 8 bit inputs changes

    Started by Mercury, 9th October 2003 20:04
    • Replies: 3
    • Views: 1,282
    19th October 2003, 07:42 Go to last post
  26. Closed: Help: design of the OPB peripheral block for PowerPC..

    Started by seamless, 16th October 2003 20:16
    • Replies: 0
    • Views: 1,152
    16th October 2003, 20:16 Go to last post
  27. Closed: attribute LOC - help needed

    Started by Vonn, 15th October 2003 09:50
    • Replies: 2
    • Views: 3,185
    16th October 2003, 20:03 Go to last post
  28. Closed: Using the NAT9914 Chip with FPGAs for GPIB design

    Started by cssheu, 15th October 2003 17:26
    • Replies: 0
    • Views: 2,184
    15th October 2003, 17:26 Go to last post
    • Replies: 1
    • Views: 1,864
    15th October 2003, 16:46 Go to last post
  29. Closed: how to simulate digital ic

    Started by ash, 10th October 2003 21:16
    • Replies: 6
    • Views: 1,547
    15th October 2003, 10:03 Go to last post