1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    92,955
Page 51 of 725 FirstFirst ... 41 49 50 51 52 53 61 101 151 551 ... LastLast
Threads 1501 to 1530 of 21746

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: AXI Stream IP in Vivado

    Started by keyboardcowboy, 26th October 2015 08:48
    • Replies: 1
    • Views: 1,017
    26th October 2015, 13:39 Go to last post
  2. Closed: Offloading for memory throughput?

    Started by Saltwater, 30th September 2015 13:39
    2 Pages
    1 2
    • Replies: 22
    • Views: 1,273
    25th October 2015, 14:06 Go to last post
  3. Closed: Approaches for calculating histograms on FPGAs

    Started by shaiko, 24th October 2015 15:36
    • Replies: 8
    • Views: 766
    24th October 2015, 23:42 Go to last post
  4. Closed: [moved] Help in writing a testbench for VHDL code

    Started by xiaoanime, 24th October 2015 06:21
    • Replies: 2
    • Views: 442
    24th October 2015, 17:08 Go to last post
  5. Closed: req: xapp369.zip from xilinx

    Started by Zerox100, 21st October 2015 17:08
    • Replies: 6
    • Views: 727
    24th October 2015, 09:27 Go to last post
  6. Closed: VHDL pwm for controlling a servo

    Started by kidi3, 23rd October 2015 17:36
    • Replies: 12
    • Views: 958
    23rd October 2015, 21:36 Go to last post
  7. Closed: Altera FPGA PLL and Serdes

    Started by shaiko, 22nd October 2015 15:26
    • Replies: 15
    • Views: 1,028
    23rd October 2015, 19:38 Go to last post
  8. Closed: NIOS II and SOPC Builder

    Started by omerysmi, 23rd October 2015 13:56
    • Replies: 6
    • Views: 416
    23rd October 2015, 16:50 Go to last post
    • Replies: 5
    • Views: 585
    23rd October 2015, 11:00 Go to last post
  9. Closed: Which FPGA chip serie is more suitable for LCD and BLU driving

    Started by Alper özel, 23rd October 2015 09:50
    • Replies: 1
    • Views: 433
    23rd October 2015, 10:40 Go to last post
  10. Closed: how to get the integer result

    Started by jkairup, 23rd October 2015 06:39
    • Replies: 2
    • Views: 405
    23rd October 2015, 08:11 Go to last post
  11. Closed: What is Fast Corner and Slow Corner?

    Started by VuTang, 23rd October 2015 03:18
    • Replies: 1
    • Views: 870
    23rd October 2015, 07:19 Go to last post
  12. Closed: Modelsim problem with signal initialization

    Started by Hugo17, 22nd October 2015 07:50
    • Replies: 5
    • Views: 607
    22nd October 2015, 22:48 Go to last post
  13. Closed: Using 2 clock inputs in a FPGA

    Started by djnik1362, 21st October 2015 06:31
    • Replies: 4
    • Views: 361
    21st October 2015, 08:55 Go to last post
  14. Closed: How to encrypt VHDL package file & synthesis with it

    Started by wesleytaylor, 20th October 2015 15:46
    • Replies: 1
    • Views: 1,142
    20th October 2015, 16:15 Go to last post
  15. Closed: why this error happened to modelsim?

    Started by JKR1, 17th October 2015 22:17
    • Replies: 1
    • Views: 516
    17th October 2015, 23:12 Go to last post
  16. Closed: Vhdl code for network on chip architecture

    Started by amin_rz, 10th October 2015 19:36
    • Replies: 3
    • Views: 701
    16th October 2015, 15:37 Go to last post
  17. Closed: what is the mechanism used for inter thread communication

    Started by bagavathi, 15th October 2015 12:51
    • Replies: 2
    • Views: 377
    15th October 2015, 20:59 Go to last post
  18. Closed: [Moved]: Write Address Collision

    Started by divya narula, 13th October 2015 19:46
    • Replies: 7
    • Views: 546
    15th October 2015, 16:16 Go to last post
  19. Closed: conversion from vhdl to verilog

    Started by meeraamrita, 15th October 2015 04:43
    • Replies: 1
    • Views: 599
    15th October 2015, 11:27 Go to last post
  20. Closed: Error: Multiple constant drivers

    Started by Hugo17, 14th October 2015 12:21
    • Replies: 5
    • Views: 760
    15th October 2015, 09:32 Go to last post
  21. Closed: Input voltage range for the FPGA

    Started by Vlad., 14th October 2015 07:20
    • Replies: 2
    • Views: 381
    14th October 2015, 07:54 Go to last post
  22. Closed: [moved] xilinx pipeline fft delay

    Started by prashanthi999, 13th October 2015 19:47
    • Replies: 2
    • Views: 587
    14th October 2015, 07:46 Go to last post
  23. Closed: mod 5 counter using jk flip flop

    Started by shalini v, 13th October 2015 08:02
    • Replies: 3
    • Views: 1,164
    13th October 2015, 16:09 Go to last post
  24. Closed: how to show this vector?

    Started by milan.km, 10th October 2015 06:29
    • Replies: 9
    • Views: 530
    13th October 2015, 15:53 Go to last post
  25. Closed: What signals are used to configure a MAX V CPLD?

    Started by matrixofdynamism, 8th October 2015 15:04
    • Replies: 13
    • Views: 880
    13th October 2015, 11:05 Go to last post
  26. [SOLVED]Closed: Problem in deserializing data on xilinx xc7z045-1-fbg676 device

    Started by punit1053, 30th September 2015 19:12
    • Replies: 7
    • Views: 1,043
    12th October 2015, 18:43 Go to last post
    • Replies: 4
    • Views: 514
    12th October 2015, 16:52 Go to last post
    • Replies: 0
    • Views: 566
    12th October 2015, 08:54 Go to last post