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Threads 1501 to 1530 of 21460

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: VHDL Simulation problem

    Started by MSAKARIM, 29th June 2015 17:26
    • Replies: 16
    • Views: 578
    2nd July 2015, 17:31 Go to last post
  2. Closed: DFF chain using a for loop

    Started by shaiko, 30th June 2015 21:44
    2 Pages
    1 2
    • Replies: 20
    • Views: 995
    FvM
    2nd July 2015, 14:11 Go to last post
  3. Closed: Ucf file conversion from virtex-2 to virtex-5

    Started by Chethan Chethu, 29th June 2015 22:40
    • Replies: 11
    • Views: 514
    1st July 2015, 23:51 Go to last post
    • Replies: 4
    • Views: 540
    1st July 2015, 16:55 Go to last post
  4. [SOLVED]Closed: Mismatches in behavioral and post PAR simulations

    Started by punit1053, 29th June 2015 12:46
    • Replies: 12
    • Views: 601
    1st July 2015, 16:34 Go to last post
  5. [SOLVED]Closed: CRC for SENT Protocol

    Started by ctzof, 29th June 2015 21:47
    • Replies: 5
    • Views: 1,474
    1st July 2015, 12:35 Go to last post
  6. Closed: Problem in Behavioral simulation of CARRY4 primitive

    Started by msdarvishi, 1st July 2015 04:02
    • Replies: 1
    • Views: 398
    1st July 2015, 07:05 Go to last post
    • Replies: 7
    • Views: 522
    1st July 2015, 04:49 Go to last post
  7. [SOLVED]Closed: FIFO o/p frequency getting reduced by 2

    Started by rahdirs, 30th June 2015 10:15
    • Replies: 3
    • Views: 325
    30th June 2015, 16:15 Go to last post
  8. Closed: Metastability in FPGAs

    Started by Tapojyoti Mandal, 30th June 2015 14:59
    • Replies: 1
    • Views: 286
    30th June 2015, 15:42 Go to last post
  9. Closed: interface FPGA to GPMC

    Started by M Subash, 30th June 2015 07:34
    • Replies: 4
    • Views: 826
    K-J
    30th June 2015, 14:11 Go to last post
  10. [SOLVED]Closed: what does this error mean??"Illegal sequential statement"

    Started by fahim1, 29th June 2015 11:22
    • Replies: 11
    • Views: 764
    30th June 2015, 09:57 Go to last post
    • Replies: 2
    • Views: 556
    30th June 2015, 09:22 Go to last post
  11. Closed: Strange behavior of Altera FIFO

    Started by shaiko, 25th June 2015 11:36
    • Replies: 14
    • Views: 1,224
    29th June 2015, 16:23 Go to last post
  12. Closed: verify functionality and calculate fmax for Altera IP

    Started by abd_elhamid_, 27th June 2015 12:10
    • Replies: 2
    • Views: 540
    28th June 2015, 10:57 Go to last post
  13. Closed: VHDL code for 8-bit synchronous reset register

    Started by manojsainadh, 27th June 2015 19:56
    • Replies: 1
    • Views: 529
    27th June 2015, 20:48 Go to last post
  14. [SOLVED]Closed: Ring oscillator desgin doesn't generate ring oscillator as wanted

    Started by kahlenberg, 26th June 2015 17:23
    • Replies: 3
    • Views: 449
    27th June 2015, 17:16 Go to last post
    • Replies: 0
    • Views: 444
    27th June 2015, 00:26 Go to last post
  15. Closed: Altera Avalon ST parameters

    Started by shaiko, 25th June 2015 22:18
    • Replies: 4
    • Views: 480
    26th June 2015, 17:08 Go to last post
    • Replies: 5
    • Views: 470
    26th June 2015, 17:00 Go to last post
  16. Closed: using abs function in vhdl

    Started by jimmykk, 26th June 2015 09:58
    • Replies: 2
    • Views: 802
    26th June 2015, 16:46 Go to last post
  17. Closed: Altera Avalon ST "emptyWithinPacket"

    Started by shaiko, 26th June 2015 12:45
    • Replies: 1
    • Views: 288
    26th June 2015, 16:06 Go to last post
  18. Closed: IP core problem while trying to create block ram

    Started by MSAKARIM, 26th June 2015 12:16
    • Replies: 0
    • Views: 291
    26th June 2015, 12:16 Go to last post
    • Replies: 8
    • Views: 2,030
    FvM
    26th June 2015, 09:34 Go to last post
  19. [SOLVED]Closed: Converting Bi directional to single directional input

    Started by ultimate_kc, 26th June 2015 05:06
    • Replies: 3
    • Views: 289
    FvM
    26th June 2015, 07:34 Go to last post
  20. Closed: Memory access two times problem

    Started by MSAKARIM, 24th June 2015 10:33
    • Replies: 14
    • Views: 416
    25th June 2015, 18:00 Go to last post
    • Replies: 1
    • Views: 410
    25th June 2015, 17:08 Go to last post
    • Replies: 3
    • Views: 364
    25th June 2015, 14:23 Go to last post
  21. [SOLVED]Closed: CMOS Image Sensor effect

    Started by sreevenkjan, 22nd May 2015 14:23
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,535
    25th June 2015, 12:38 Go to last post
  22. Closed: VHDL unsigned to signed conversion.

    Started by zoulzubazz, 25th June 2015 11:21
    • Replies: 4
    • Views: 797
    25th June 2015, 12:26 Go to last post

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