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Threads 1501 to 1530 of 21629

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: PCI with FPGA spartan 3 or 6

    Started by amin5659, 21st August 2015 20:15
    • Replies: 7
    • Views: 759
    2nd September 2015, 16:34 Go to last post
  2. Closed: Websites magazines for professional FPGA designers

    Started by matrixofdynamism, 28th August 2015 22:57
    • Replies: 3
    • Views: 573
    2nd September 2015, 15:40 Go to last post
  3. Closed: An accurate seconds counter in VHDL

    Started by omerysmi, 30th August 2015 15:19
    • Replies: 5
    • Views: 787
    1st September 2015, 21:07 Go to last post
  4. Closed: Which is better - VHDL or Verilog

    Started by garvind25, 28th August 2015 18:47
    • Replies: 7
    • Views: 604
    1st September 2015, 12:37 Go to last post
  5. Closed: [Moved]: splitting up signal paths "logic"

    Started by Saltwater, 30th August 2015 19:54
    • Replies: 6
    • Views: 620
    31st August 2015, 16:44 Go to last post
  6. [SOLVED]Closed: spartan 3E LCD verilog problem??

    Started by Hafeez Ur Rehman, 26th August 2015 19:42
    • Replies: 1
    • Views: 648
    30th August 2015, 18:09 Go to last post
  7. [SOLVED]Closed: How to write constrain for spi interface

    Started by brainiac_rus, 30th August 2015 11:22
    • Replies: 3
    • Views: 996
    30th August 2015, 13:29 Go to last post
  8. Closed: VHDL Type duplicate definition in different file, won't connect?

    Started by legendbb, 28th August 2015 19:54
    • Replies: 4
    • Views: 652
    30th August 2015, 00:50 Go to last post
    • Replies: 1
    • Views: 635
    29th August 2015, 22:34 Go to last post
  9. Closed: Access DLL files from FPGA

    Started by marufsust, 24th August 2015 11:50
    • Replies: 3
    • Views: 617
    29th August 2015, 10:58 Go to last post
    • Replies: 5
    • Views: 763
    29th August 2015, 04:15 Go to last post
  10. Closed: why I have this fatal error?

    Started by JKR1, 28th August 2015 08:38
    • Replies: 11
    • Views: 486
    28th August 2015, 11:53 Go to last post
  11. [SOLVED]Closed: counting pulses in one second with vhdl

    Started by sam93, 23rd July 2015 14:43
    2 Pages
    1 2
    • Replies: 29
    • Views: 3,629
    28th August 2015, 09:35 Go to last post
  12. [MOVED] Image processing and VHDL

    Started by lamrita, 8th December 2007 22:14
    • Replies: 2
    • Views: 1,508
    27th August 2015, 07:15 Go to last post
  13. [SOLVED]Closed: Fatal error in modelsim

    Started by esielec, 26th August 2015 15:25
    • Replies: 8
    • Views: 1,380
    27th August 2015, 05:50 Go to last post
  14. Closed: is it posible to label entity in vhdl ?

    Started by aruipksni, 26th August 2015 10:17
    • Replies: 1
    • Views: 389
    26th August 2015, 14:59 Go to last post
  15. Closed: Microblaze integration problems

    Started by efontesp, 25th August 2015 21:43
    • Replies: 2
    • Views: 505
    26th August 2015, 10:39 Go to last post
  16. Closed: How to bring an internal signal of a module into test bench ?

    Started by msdarvishi, 25th August 2015 00:43
    • Replies: 8
    • Views: 854
    26th August 2015, 07:58 Go to last post
  17. Closed: Error: Index <8> is out of range [0:7] for signal <ram>.

    Started by QMA, 25th August 2015 18:01
    • Replies: 2
    • Views: 710
    25th August 2015, 21:11 Go to last post
  18. Closed: how to read video with FPGA?

    Started by JKR1, 24th August 2015 11:25
    • Replies: 8
    • Views: 915
    25th August 2015, 21:06 Go to last post
  19. Closed: How tristate2logic works in xilinx fpga's

    Started by hulk789, 25th August 2015 13:23
    • Replies: 1
    • Views: 416
    25th August 2015, 13:37 Go to last post
  20. [SOLVED]Closed: how to assign the following array

    Started by hulk789, 24th August 2015 13:39
    • Replies: 3
    • Views: 443
    24th August 2015, 21:53 Go to last post
    • Replies: 4
    • Views: 743
    24th August 2015, 10:22 Go to last post
  21. Closed: Pl and Peripheral interaction on Zynq SoC

    Started by ismailov-e, 24th August 2015 06:07
    • Replies: 0
    • Views: 354
    24th August 2015, 06:07 Go to last post
  22. [SOLVED]Closed: Power Consumption of Emulated MCUs

    Started by BurnAndLearn, 21st August 2015 16:13
    • Replies: 7
    • Views: 482
    22nd August 2015, 05:40 Go to last post
  23. Closed: alternate of for loop

    Started by QMA, 21st August 2015 12:35
    • Replies: 16
    • Views: 542
    22nd August 2015, 03:47 Go to last post
  24. Closed: Signed Integer Division VHDL

    Started by ranbi, 13th March 2012 16:37
    • Replies: 5
    • Views: 2,523
    22nd August 2015, 03:35 Go to last post
  25. Closed: "Read Before Write" RAM

    Started by shaiko, 20th August 2015 09:28
    • Replies: 12
    • Views: 1,325
    22nd August 2015, 03:33 Go to last post
  26. Closed: Random clock period in a FPGA

    Started by Binome, 21st August 2015 09:44
    • Replies: 5
    • Views: 383
    21st August 2015, 15:44 Go to last post
  27. Closed: Use generic in package: VHDL

    Started by jeetesh, 21st August 2015 10:33
    • Replies: 5
    • Views: 1,843
    21st August 2015, 11:51 Go to last post