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Threads 1501 to 1530 of 21841

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: [Moved] Verilog : can "initial" be used in main module?

    Started by jesslyn993, 3rd December 2015 08:09
    • Replies: 2
    • Views: 334
    3rd December 2015, 08:40 Go to last post
  2. Closed: error in a<=postponed b after 10ns;

    Started by hulk789, 3rd December 2015 06:15
    • Replies: 1
    • Views: 357
    3rd December 2015, 07:15 Go to last post
  3. Closed: transformation length problem of FFT in VHDL

    Started by habbas33, 2nd December 2015 08:49
    • Replies: 1
    • Views: 362
    2nd December 2015, 12:32 Go to last post
  4. Closed: Detecting a pattern in a parallel bus random start bit

    Started by troy99xx, 30th November 2015 21:40
    2 Pages
    1 2
    • Replies: 27
    • Views: 1,299
    2nd December 2015, 07:50 Go to last post
  5. Closed: Can not generate Verilog using FIFO Generator in IP catalog

    Started by slutarius, 1st December 2015 09:04
    • Replies: 5
    • Views: 688
    2nd December 2015, 02:29 Go to last post
  6. Closed: Simplification of Boolean Expression

    Started by blade88, 9th October 2015 22:10
    • Replies: 3
    • Views: 633
    1st December 2015, 02:50 Go to last post
  7. Closed: code vhdl for multiplication matrix .. need hekp

    Started by napiuuul, 29th November 2015 06:52
    • Replies: 8
    • Views: 861
    30th November 2015, 18:16 Go to last post
  8. Closed: How to use JTAG pin as I/O in Altera

    Started by Manpreet1604, 30th November 2015 10:40
    • Replies: 1
    • Views: 379
    30th November 2015, 11:32 Go to last post
  9. Closed: Vhdl code for square ?

    Started by napiuuul, 26th November 2015 11:01
    • Replies: 6
    • Views: 1,525
    27th November 2015, 21:07 Go to last post
  10. [SOLVED]Closed: Simulating clock frequencies of a PLL - error due to rounding?

    Started by LatticeSemiconductor, 27th November 2015 12:20
    • Replies: 2
    • Views: 323
    27th November 2015, 13:43 Go to last post
  11. Closed: Reading byte by byte from a register

    Started by beginner_EDA, 27th November 2015 10:27
    • Replies: 2
    • Views: 315
    27th November 2015, 11:10 Go to last post
  12. Closed: customise prortocol in wireshark

    Started by gobiraj, 26th November 2015 14:51
    • Replies: 0
    • Views: 316
    26th November 2015, 14:51 Go to last post
  13. Closed: please provide a solution for Timing Diagram

    Started by Anupama shetter, 26th November 2015 10:57
    • Replies: 1
    • Views: 424
    26th November 2015, 14:34 Go to last post
  14. [SOLVED]Closed: Error in Vhdl Questa(10.b) Simulation: "No default binding for component at"

    Started by Eligineer, 25th November 2015 14:09
    • Replies: 0
    • Views: 406
    25th November 2015, 14:09 Go to last post
    • Replies: 8
    • Views: 1,402
    24th November 2015, 21:49 Go to last post
  15. Closed: Gated Clock in Altera

    Started by ivlsi, 24th November 2015 10:33
    • Replies: 3
    • Views: 612
    24th November 2015, 21:22 Go to last post
  16. [SOLVED]Closed: Interfacing a Spartan 3E xps_iic to an external peripheral through I2C bus.

    Started by Yosmany325, 17th November 2015 14:37
    • Replies: 4
    • Views: 448
    24th November 2015, 14:16 Go to last post
  17. Closed: Loading default values to block RAM using Quartus

    Started by shaiko, 22nd November 2015 17:37
    • Replies: 9
    • Views: 692
    24th November 2015, 06:31 Go to last post
  18. Closed: Please help me to write a VERILOG code for MODULO 14 counter

    Started by bynx1234, 22nd November 2015 19:40
    • Replies: 2
    • Views: 1,016
    23rd November 2015, 17:19 Go to last post
  19. Closed: interfacing virtex-5 ml505 xc5vlx110t board with ise 14.7

    Started by jutkarsh079, 22nd November 2015 20:43
    • Replies: 1
    • Views: 512
    23rd November 2015, 17:16 Go to last post
  20. Closed: Constraning an asynchronous design

    Started by shaiko, 20th November 2015 21:36
    2 Pages
    1 2
    • Replies: 22
    • Views: 1,234
    23rd November 2015, 17:10 Go to last post
  21. Closed: Image and Video processing implementation in FPGA

    Started by beginner_EDA, 21st November 2015 20:56
    • Replies: 4
    • Views: 652
    23rd November 2015, 16:45 Go to last post
  22. Closed: Problem with ISE 14.7 SDK

    Started by Zarrin, 23rd November 2015 13:16
    • Replies: 0
    • Views: 524
    23rd November 2015, 13:16 Go to last post
    • Replies: 1
    • Views: 280
    23rd November 2015, 10:34 Go to last post
  23. Closed: 64b/66b encoding and decoding

    Started by sh.akhtari, 21st November 2015 09:55
    • Replies: 1
    • Views: 568
    21st November 2015, 10:25 Go to last post
    • Replies: 1
    • Views: 323
    20th November 2015, 16:48 Go to last post
  24. Closed: [Moved]: display 640x480 at 30fps though VGA

    Started by franofcholet, 20th November 2015 16:31
    • Replies: 2
    • Views: 374
    20th November 2015, 16:45 Go to last post
  25. Closed: Applications of SRAM and SDRAM found in FPGA boads

    Started by matrixofdynamism, 18th November 2015 16:14
    • Replies: 4
    • Views: 461
    20th November 2015, 15:13 Go to last post
  26. Closed: 16-bit Processor's ALU Design in Verilog

    Started by tarjina, 19th November 2015 18:33
    • Replies: 6
    • Views: 1,126
    20th November 2015, 12:15 Go to last post
  27. Closed: A concept about State Machine using process in VHDL

    Started by beginner_EDA, 17th November 2015 17:10
    • Replies: 16
    • Views: 876
    20th November 2015, 06:15 Go to last post