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Threads 15001 to 15030 of 21746

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: FPGA is required??????????

    Started by Sahara, 20th March 2008 04:02
    • Replies: 3
    • Views: 652
    20th March 2008, 10:48 Go to last post
    • Replies: 4
    • Views: 8,625
    20th March 2008, 10:40 Go to last post
  2. Closed: Problem with a code for assigning RAM location

    Started by anandanips, 20th March 2008 09:26
    • Replies: 2
    • Views: 828
    20th March 2008, 10:35 Go to last post
  3. Closed: How to write VHDL code for asynchronous FSM?

    Started by ztanish, 20th March 2008 04:50
    • Replies: 0
    • Views: 991
    20th March 2008, 04:50 Go to last post
    • Replies: 2
    • Views: 1,307
    19th March 2008, 07:31 Go to last post
  4. Closed: final project about FPPAs

    Started by omar-malek, 19th March 2008 01:22
    • Replies: 1
    • Views: 638
    19th March 2008, 02:01 Go to last post
  5. Closed: EDK with Spartan 3E Starter Kit

    Started by Rob B, 18th March 2008 03:00
    • Replies: 4
    • Views: 2,908
    18th March 2008, 19:12 Go to last post
  6. Closed: XST 1710 warning in VHDL code for VGA interface

    Started by BlackOps, 16th March 2008 23:08
    • Replies: 1
    • Views: 1,831
    18th March 2008, 10:08 Go to last post
  7. Closed: query abt FMAP AND HMAP

    Started by abhi_459, 18th March 2008 09:45
    • Replies: 0
    • Views: 522
    18th March 2008, 09:45 Go to last post
    • Replies: 1
    • Views: 1,528
    18th March 2008, 08:25 Go to last post
  8. Closed: active low reset or active high reset

    Started by dinesh.4126, 10th March 2008 07:34
    • Replies: 16
    • Views: 2,113
    17th March 2008, 18:40 Go to last post
  9. Closed: Recommend me a high level synthesis tools for FPGA

    Started by asoom, 16th March 2008 21:22
    • Replies: 5
    • Views: 880
    17th March 2008, 18:18 Go to last post
  10. Closed: FPGA techniques question

    Started by 555lin, 17th March 2008 14:22
    • Replies: 0
    • Views: 743
    17th March 2008, 14:22 Go to last post
  11. Closed: How to include Virtex2 Pro Library in my design?

    Started by BlackOps, 13th March 2008 19:25
    • Replies: 12
    • Views: 1,866
    17th March 2008, 13:34 Go to last post
  12. Closed: How can I determine the order of FIR filter if it has 8-taps?

    Started by reninroy, 17th March 2008 12:55
    • Replies: 0
    • Views: 956
    17th March 2008, 12:55 Go to last post
  13. Closed: timing constraints in multipliers

    Started by samiksha, 14th March 2008 06:39
    • Replies: 8
    • Views: 921
    17th March 2008, 10:58 Go to last post
  14. Closed: FPGA for DSP coprocessing duties, addr/data bus...

    Started by vandelay, 17th March 2008 06:10
    • Replies: 0
    • Views: 900
    17th March 2008, 06:10 Go to last post
  15. Closed: 22v10 programmer needed...!!!

    Started by hussain_kiet, 14th March 2008 06:48
    • Replies: 4
    • Views: 3,950
    17th March 2008, 05:05 Go to last post
  16. Closed: EDK and GDB - Code does not run

    Started by Rob B, 13th March 2008 16:55
    • Replies: 6
    • Views: 1,440
    16th March 2008, 18:18 Go to last post
  17. Closed: Help me edit m file code for the black box

    Started by r_a_c_a_4_u, 16th March 2008 16:19
    • Replies: 0
    • Views: 724
    16th March 2008, 16:19 Go to last post
  18. Closed: I want phase shift in DDS output depending upon the input

    Started by r_a_c_a_4_u, 16th March 2008 06:18
    • Replies: 2
    • Views: 1,200
    16th March 2008, 15:21 Go to last post
  19. Closed: Chipscope analyzer problem with buffered data

    Started by ehsan_iut, 13th March 2008 16:42
    • Replies: 5
    • Views: 1,085
    16th March 2008, 13:26 Go to last post
  20. Closed: How to implement y=sinx in VHDL?

    Started by sachinmaheshwari, 13th March 2008 13:15
    • Replies: 13
    • Views: 2,943
    16th March 2008, 12:50 Go to last post
  21. Closed: hardware speed vs software speed

    Started by anandanips, 13th March 2008 08:28
    • Replies: 8
    • Views: 1,856
    16th March 2008, 09:01 Go to last post
  22. Closed: How to do place and route in SOC Encounter

    Started by sachinmaheshwari, 15th March 2008 19:18
    • Replies: 0
    • Views: 723
    15th March 2008, 19:18 Go to last post
  23. Closed: frequency multiplier on fpga

    Started by rave1786, 9th March 2008 19:50
    • Replies: 4
    • Views: 2,561
    15th March 2008, 17:31 Go to last post
  24. Closed: delay in timesim simulation in Modelsim

    Started by gck, 14th March 2008 06:40
    • Replies: 3
    • Views: 1,240
    15th March 2008, 17:05 Go to last post
  25. Closed: not able to generate sine wave using DDS in simulink

    Started by r_a_c_a_4_u, 14th March 2008 13:36
    • Replies: 1
    • Views: 3,056
    15th March 2008, 12:27 Go to last post
  26. Closed: problem about coregen

    Started by taolibuyan, 13th December 2007 15:06
    • Replies: 3
    • Views: 1,748
    15th March 2008, 08:35 Go to last post
  27. Closed: How to implement Divisio Function on Xilinix V4 ?

    Started by omara007, 15th March 2008 02:11
    • Replies: 1
    • Views: 689
    15th March 2008, 08:21 Go to last post