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Threads 15001 to 15030 of 21460

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Can we assign the integer value on input pins of Spartan-3 ?

    Started by abhi_459, 23rd January 2008 10:26
    • Replies: 14
    • Views: 1,313
    4th February 2008, 05:03 Go to last post
  2. Closed: Looking for basic resources on I2C Bus

    Started by sameem_shabbir, 2nd February 2008 05:44
    • Replies: 7
    • Views: 1,415
    FvM
    3rd February 2008, 19:58 Go to last post
  3. Closed: Benchmark circuits.....

    Started by angu, 3rd February 2008 14:47
    • Replies: 0
    • Views: 1,952
    3rd February 2008, 14:47 Go to last post
  4. Closed: Help LCD for FPGA starter kit

    Started by neyadi, 1st February 2008 03:46
    • Replies: 5
    • Views: 1,144
    2nd February 2008, 17:45 Go to last post
  5. Closed: Networks on Chip Implementation of SNI

    Started by anuragjain, 1st February 2008 19:11
    • Replies: 1
    • Views: 602
    2nd February 2008, 07:52 Go to last post
  6. Closed: How to convert Verilog code to block diagram or schematics?

    Started by mhamed, 30th January 2008 20:09
    • Replies: 5
    • Views: 9,097
    2nd February 2008, 01:54 Go to last post
  7. Closed: I need help with understanding Xilinx tools

    Started by mharries, 1st February 2008 07:48
    • Replies: 4
    • Views: 780
    1st February 2008, 18:12 Go to last post
  8. Closed: HELP >>> XESS Board User

    Started by sameem_shabbir, 1st February 2008 16:31
    • Replies: 0
    • Views: 578
    1st February 2008, 16:31 Go to last post
  9. Closed: Free pdf resource file for VirSim

    Started by daniel_shk, 1st February 2008 15:14
    • Replies: 0
    • Views: 598
    1st February 2008, 15:14 Go to last post
  10. Closed: cpld fpga starting.......

    Started by marwan naboulsi, 1st February 2008 10:45
    • Replies: 1
    • Views: 722
    1st February 2008, 12:19 Go to last post
    • Replies: 1
    • Views: 1,798
    FvM
    1st February 2008, 10:51 Go to last post
  11. Closed: iteration limit in verilog

    Started by simu, 1st February 2008 10:10
    • Replies: 0
    • Views: 1,674
    1st February 2008, 10:10 Go to last post
  12. Closed: coding for SYNCHRONOUS FIFO implementation with diff clocks?

    Started by dav, 31st January 2008 12:07
    • Replies: 6
    • Views: 1,454
    1st February 2008, 04:41 Go to last post
  13. Closed: Is there a delay element in Xilinx FPGAs or CPLDs?

    Started by Zerox100, 26th January 2008 05:13
    • Replies: 7
    • Views: 3,512
    1st February 2008, 04:39 Go to last post
  14. Closed: How can i instance one DCM in my design?

    Started by Zerox100, 26th January 2008 05:23
    • Replies: 6
    • Views: 1,175
    1st February 2008, 04:38 Go to last post
  15. Closed: programming CY7C68013A in mcs51 assembly???

    Started by volkantr, 31st January 2008 09:11
    • Replies: 2
    • Views: 1,760
    FvM
    31st January 2008, 22:43 Go to last post
  16. Closed: ALDEC Opinion vs modelsim?

    Started by mImoto, 22nd January 2008 07:50
    • Replies: 3
    • Views: 4,219
    31st January 2008, 16:46 Go to last post
  17. Closed: Questions about pipelined array multiplier

    Started by hbsustc, 29th January 2008 01:14
    • Replies: 9
    • Views: 4,022
    31st January 2008, 15:28 Go to last post
  18. Closed: fft(8192point ) in fpga

    Started by AIDIN.RM, 21st June 2006 21:51
    • Replies: 6
    • Views: 1,941
    31st January 2008, 08:46 Go to last post
  19. Closed: Problem with installing ModelSim

    Started by atena, 25th January 2008 11:35
    • Replies: 7
    • Views: 3,957
    31st January 2008, 03:36 Go to last post
  20. Closed: Synplify vs Xilinx ISE

    Started by gliss, 19th December 2007 14:18
    • Replies: 13
    • Views: 9,501
    30th January 2008, 18:42 Go to last post
  21. Closed: .ucf to Xilinx Platform Studio

    Started by bLurLiNg88, 17th January 2008 01:32
    • Replies: 5
    • Views: 4,896
    30th January 2008, 18:35 Go to last post
  22. Closed: question regarding on output offset

    Started by cherjier, 22nd January 2008 11:38
    • Replies: 10
    • Views: 1,213
    30th January 2008, 16:02 Go to last post
  23. Closed: help in selecting level shifter IC

    Started by sita, 27th January 2008 15:23
    • Replies: 7
    • Views: 6,165
    30th January 2008, 12:33 Go to last post
  24. Closed: I need help with the twiddle factor in Verilog

    Started by neefa, 30th January 2008 06:07
    • Replies: 1
    • Views: 1,498
    30th January 2008, 07:55 Go to last post
  25. Closed: Can the GSM module be realized by a FPGA chip?

    Started by staraimm, 29th January 2008 08:56
    • Replies: 7
    • Views: 2,135
    30th January 2008, 06:10 Go to last post
  26. Closed: ANY BODY doing C Synthesis??

    Started by eltonjohn, 10th April 2007 03:22
    • Replies: 3
    • Views: 1,160
    30th January 2008, 04:36 Go to last post
  27. Closed: I wonder if C synthesis can be considered as behavioral?

    Started by eltonjohn, 8th April 2007 17:25
    • Replies: 1
    • Views: 821
    30th January 2008, 04:35 Go to last post
  28. Closed: are there any visual C++ to VHDL converter out there?

    Started by Nyceane, 13th April 2006 23:39
    • Replies: 11
    • Views: 6,771
    30th January 2008, 04:35 Go to last post
  29. Closed: replace ps/2 to RS-232 module?

    Started by ggniy, 29th January 2008 10:01
    • Replies: 2
    • Views: 1,126
    30th January 2008, 01:51 Go to last post