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Threads 61 to 90 of 21736

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] How to have an undefined range in function?

    Started by wesleytaylor, 26th June 2017 13:49
    • Replies: 3
    • Views: 456
    27th June 2017, 10:09 Go to last post
  2. Real life throughput of FPGA DSP blocks

    Started by shaiko, 24th June 2017 15:15
    • Replies: 10
    • Views: 753
    27th June 2017, 04:56 Go to last post
  3. Reading numbers and assign them to an array

    Started by mahmood.n, 23rd June 2017 10:48
    • Replies: 13
    • Views: 1,054
    25th June 2017, 18:55 Go to last post
    • Replies: 6
    • Views: 682
    22nd June 2017, 11:28 Go to last post
    • Replies: 1
    • Views: 260
    22nd June 2017, 11:24 Go to last post
    • Replies: 3
    • Views: 354
    22nd June 2017, 10:03 Go to last post
  4. Moved: serial port demo program working.. but nothing in terminal

    Started by dipin, 5th July 2017 12:56
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  5. 4 to 11 Decoder in VerilogA

    Started by PaulineVi, 21st June 2017 14:59
    • Replies: 6
    • Views: 471
    21st June 2017, 18:58 Go to last post
  6. VHDL Comparison Tree

    Started by shaiko, 18th June 2017 17:48
    • Replies: 18
    • Views: 1,379
    21st June 2017, 07:56 Go to last post
  7. USB blaster fail to work after Quartus update

    Started by mahmood.n, 20th June 2017 16:48
    • Replies: 3
    • Views: 521
    20th June 2017, 23:56 Go to last post
    • Replies: 1
    • Views: 323
    20th June 2017, 14:46 Go to last post
  8. send/receive data to/from fpga device

    Started by mahmood.n, 16th June 2017 09:24
    • Replies: 11
    • Views: 1,110
    17th June 2017, 09:32 Go to last post
    • Replies: 4
    • Views: 420
    17th June 2017, 00:42 Go to last post
  9. Single multiplier takes up a whole DSP block for

    Started by shaiko, 14th June 2017 15:51
    • Replies: 13
    • Views: 919
    16th June 2017, 08:54 Go to last post
  10. Quartus not show the port size correctly

    Started by mahmood.n, 15th June 2017 23:12
    • Replies: 2
    • Views: 507
    16th June 2017, 07:43 Go to last post
  11. simulation-based faults injection

    Started by ouij, 12th June 2017 11:23
    • Replies: 7
    • Views: 694
    15th June 2017, 15:41 Go to last post
  12. binary dividing: restoring method

    Started by kk_0, 13th June 2017 20:32
    • Replies: 3
    • Views: 542
    14th June 2017, 22:22 Go to last post
    • Replies: 3
    • Views: 774
    14th June 2017, 18:01 Go to last post
  13. PWM for LED module to choose duty cycle

    Started by manush30, 28th May 2017 14:22
    • Replies: 6
    • Views: 894
    14th June 2017, 17:34 Go to last post
  14. Register vs BRAM vs slice count

    Started by Tarunfpga1, 13th June 2017 08:58
    • Replies: 1
    • Views: 346
    13th June 2017, 19:04 Go to last post
  15. How to work out with "inout" port in verilog?

    Started by hcu, 13th June 2017 06:41
    • Replies: 8
    • Views: 525
    13th June 2017, 18:46 Go to last post
  16. Temperature and Voltage Monitoring using XADC

    Started by beginner_EDA, 13th June 2017 14:29
    • Replies: 1
    • Views: 272
    13th June 2017, 16:16 Go to last post
    • Replies: 4
    • Views: 726
    13th June 2017, 16:13 Go to last post
  17. A pseudo-random number generator

    Started by Binome, 13th June 2017 10:25
    • Replies: 4
    • Views: 273
    13th June 2017, 14:15 Go to last post
  18. WARNING:NgdBuild:486 in xilinx

    Started by ecasha, 13th June 2017 04:25
    • Replies: 1
    • Views: 314
    13th June 2017, 08:46 Go to last post
  19. [SOLVED] FPGA: Different behavior after synthesis

    Started by birbal, 12th June 2017 22:23
    • Replies: 4
    • Views: 437
    12th June 2017, 23:42 Go to last post
  20. Route 455: CLK Net may have excessive skew

    Started by sonika111, 12th June 2017 15:58
    • Replies: 1
    • Views: 306
    12th June 2017, 17:53 Go to last post
  21. I2C with Picoblaze processor

    Started by beginner_EDA, 7th June 2017 11:33
    • Replies: 2
    • Views: 562
    12th June 2017, 09:41 Go to last post
    • Replies: 4
    • Views: 598
    12th June 2017, 07:59 Go to last post
  22. Using a component in loop

    Started by mahmood.n, 10th June 2017 10:34
    • Replies: 6
    • Views: 963
    11th June 2017, 14:20 Go to last post