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Threads 61 to 90 of 21623

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Critical path of combinational circuit

    Started by mahmood.n, 30th March 2017 13:11
    • Replies: 10
    • Views: 482
    6th May 2017, 07:17 Go to last post
  2. Timing Delay in FPGA

    Started by dzafar, 5th May 2017 22:57
    • Replies: 5
    • Views: 237
    6th May 2017, 01:41 Go to last post
    • Replies: 2
    • Views: 309
    5th May 2017, 20:14 Go to last post
    • Replies: 10
    • Views: 701
    5th May 2017, 13:58 Go to last post
  3. Programmed DE0 doesn't work

    Started by mahmood.n, 4th May 2017 11:19
    • Replies: 2
    • Views: 188
    4th May 2017, 15:32 Go to last post
  4. [SOLVED] VHDL - what is vmode ? a keyword i've never heard of?

    Started by wesleytaylor, 3rd May 2017 14:02
    • Replies: 5
    • Views: 405
    4th May 2017, 13:53 Go to last post
  5. [SOLVED] [moved] Embedded Memory Blocks in FPGA

    Started by dzafar, 25th April 2017 06:43
    • Replies: 4
    • Views: 454
    3rd May 2017, 23:00 Go to last post
  6. using variables or signals in procedure

    Started by mahmood.n, 2nd May 2017 09:35
    • Replies: 1
    • Views: 191
    2nd May 2017, 10:07 Go to last post
  7. [SOLVED] Using range is slv case statement

    Started by wesleytaylor, 2nd May 2017 09:26
    • Replies: 1
    • Views: 238
    2nd May 2017, 09:57 Go to last post
    • Replies: 0
    • Views: 141
    2nd May 2017, 07:55 Go to last post
  8. Moved: Shift Register and Serial-In Parallel Out converter

    Started by mwb, 1st May 2017 00:47
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  9. [moved] MATLAB,Xilinx ISE inteface

    Started by ecasha, 1st May 2017 09:54
    • Replies: 0
    • Views: 187
    1st May 2017, 09:54 Go to last post
  10. [SOLVED] Lattice LC4064V Programmer need help !!! Thanks bros.

    Started by makeup4u, 27th April 2017 17:05
    • Replies: 8
    • Views: 489
    30th April 2017, 10:57 Go to last post
  11. Simulation of latch with concurrent statements

    Started by mahmood.n, 29th April 2017 09:09
    • Replies: 2
    • Views: 427
    29th April 2017, 18:58 Go to last post
  12. Problem in Verilog Array

    Started by manik045, 29th April 2017 12:47
    • Replies: 1
    • Views: 203
    29th April 2017, 15:39 Go to last post
    • Replies: 7
    • Views: 608
    29th April 2017, 08:22 Go to last post
  13. Help on timing closure

    Started by LatticeSemiconductor, 27th April 2017 10:13
    • Replies: 6
    • Views: 387
    29th April 2017, 05:13 Go to last post
  14. [SOLVED] vhdl coding for pipo and testbench

    Started by marzhan, 28th April 2017 08:43
    • Replies: 4
    • Views: 327
    28th April 2017, 23:13 Go to last post
    • Replies: 3
    • Views: 214
    28th April 2017, 16:06 Go to last post
    • Replies: 3
    • Views: 302
    28th April 2017, 11:52 Go to last post
  15. Implementing logic in ram

    Started by NovNov, 25th April 2017 16:10
    • Replies: 10
    • Views: 424
    27th April 2017, 23:23 Go to last post
  16. Ram accessing through VHDL code.

    Started by abhijithr1, 27th April 2017 08:27
    • Replies: 2
    • Views: 204
    27th April 2017, 11:49 Go to last post
    • Replies: 1
    • Views: 185
    27th April 2017, 07:05 Go to last post
    • Replies: 0
    • Views: 166
    27th April 2017, 05:09 Go to last post
  17. Flip Flop Memory in FPGA: Read Write Ports

    Started by dzafar, 27th April 2017 00:38
    • Replies: 1
    • Views: 185
    27th April 2017, 01:04 Go to last post
  18. Generate 40 Hz from 44MHz clock

    Started by dhan_pow, 21st April 2017 05:33
    • Replies: 3
    • Views: 299
    26th April 2017, 16:16 Go to last post
  19. using if statement in verilog

    Started by emerson_11, 21st April 2017 05:22
    • Replies: 7
    • Views: 445
    26th April 2017, 14:20 Go to last post
  20. [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    Started by roshan12, 19th April 2017 05:39
    • Replies: 5
    • Views: 517
    26th April 2017, 07:25 Go to last post
  21. [SOLVED] vhdl FSM lockout, lazy approach to fix

    Started by wesleytaylor, 24th April 2017 14:13
    • Replies: 7
    • Views: 390
    25th April 2017, 23:27 Go to last post