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Threads 31 to 60 of 21623

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Minus sign for synthesis

    Started by mahmood.n, 15th May 2017 18:34
    • Replies: 6
    • Views: 268
    16th May 2017, 00:28 Go to last post
  2. [SOLVED] Statement inside CASE in VHDL

    Started by dzafar, 15th May 2017 08:28
    • Replies: 4
    • Views: 274
    15th May 2017, 19:32 Go to last post
  3. Problem with "find_routing_path" command in Tcl

    Started by msdarvishi, 15th March 2017 20:58
    • Replies: 8
    • Views: 428
    15th May 2017, 18:46 Go to last post
  4. Deference between soc and soft processor

    Started by sala77, 15th May 2017 09:28
    • Replies: 1
    • Views: 181
    15th May 2017, 12:44 Go to last post
  5. Motor control by FPGA

    Started by sala77, 15th May 2017 09:14
    • Replies: 2
    • Views: 168
    15th May 2017, 10:17 Go to last post
  6. [SOLVED] Integer to Natural Type Casting in VHDL

    Started by dzafar, 15th May 2017 07:38
    • Replies: 5
    • Views: 202
    15th May 2017, 10:00 Go to last post
  7. Need Help regarding Actel FPGA Area Constraints

    Started by saad_sipra, 10th May 2017 16:06
    • Replies: 14
    • Views: 1,249
    14th May 2017, 02:50 Go to last post
    • Replies: 3
    • Views: 276
    12th May 2017, 22:58 Go to last post
  8. Synchronous input FSM & sensitivity list

    Started by Kaskode, 2nd May 2017 12:25
    2 Pages
    1 2
    • Replies: 25
    • Views: 1,661
    12th May 2017, 22:42 Go to last post
    • Replies: 3
    • Views: 244
    12th May 2017, 04:40 Go to last post
    • Replies: 4
    • Views: 224
    12th May 2017, 01:40 Go to last post
    • Replies: 12
    • Views: 515
    11th May 2017, 17:00 Go to last post
  9. [SOLVED] Synthesizing clk delay : Verilog functional code

    Started by ashrafsazid, 11th May 2017 00:13
    • Replies: 6
    • Views: 408
    11th May 2017, 16:37 Go to last post
    • Replies: 8
    • Views: 505
    10th May 2017, 21:41 Go to last post
  10. 0 definitions of operator "+" match here [ERROR]

    Started by Cousin, 10th May 2017 04:28
    • Replies: 3
    • Views: 239
    10th May 2017, 11:38 Go to last post
  11. Pal to vga converter

    Started by Bar Ettdgui, 12th March 2017 07:04
    • Replies: 14
    • Views: 664
    10th May 2017, 09:13 Go to last post
    • Replies: 3
    • Views: 243
    9th May 2017, 20:37 Go to last post
  12. Piplelining for critical path delay

    Started by dzafar, 8th May 2017 08:51
    • Replies: 8
    • Views: 556
    9th May 2017, 16:37 Go to last post
  13. simulation of array of integers

    Started by mahmood.n, 8th May 2017 16:20
    • Replies: 1
    • Views: 180
    8th May 2017, 16:31 Go to last post
  14. Practical Issues in Critical Timing

    Started by dzafar, 8th May 2017 09:38
    • Replies: 1
    • Views: 156
    8th May 2017, 11:21 Go to last post
  15. Flip Flop Timing Constraints

    Started by dzafar, 6th May 2017 23:24
    • Replies: 8
    • Views: 493
    8th May 2017, 11:19 Go to last post
  16. [SOLVED] libero tcl script not working

    Started by wesleytaylor, 5th May 2017 11:04
    • Replies: 2
    • Views: 318
    8th May 2017, 09:05 Go to last post
  17. Specialized calculator using VHDL

    Started by NightOWL, 1st May 2017 20:59
    • Replies: 8
    • Views: 704
    7th May 2017, 21:07 Go to last post
  18. Video overlay in VHDL

    Started by filip.amator, 30th April 2017 18:29
    • Replies: 7
    • Views: 367
    7th May 2017, 20:08 Go to last post
  19. Programming FPGA thorough UART port ?

    Started by doost4, 1st May 2017 11:23
    • Replies: 7
    • Views: 525
    7th May 2017, 00:36 Go to last post
  20. Negative array index

    Started by mahmood.n, 6th May 2017 15:28
    • Replies: 2
    • Views: 186
    6th May 2017, 21:16 Go to last post
  21. An experiment at vivado verilog

    Started by elessar95, 5th May 2017 21:46
    • Replies: 3
    • Views: 217
    6th May 2017, 20:00 Go to last post
    • Replies: 0
    • Views: 222
    6th May 2017, 11:36 Go to last post
  22. communication with pc fro fpga

    Started by dipin, 8th April 2017 08:40
    • Replies: 7
    • Views: 787
    6th May 2017, 08:54 Go to last post