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Threads 31 to 60 of 21460

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] MIG FIFO Requirement

    Started by pcmistic, 18th March 2017 15:35
    • Replies: 2
    • Views: 241
    19th March 2017, 12:56 Go to last post
    • Replies: 7
    • Views: 318
    17th March 2017, 16:24 Go to last post
    • Replies: 1
    • Views: 170
    17th March 2017, 10:39 Go to last post
  2. Problem with "find_routing_path" command in Tcl

    Started by msdarvishi, 15th March 2017 20:58
    • Replies: 3
    • Views: 200
    16th March 2017, 00:45 Go to last post
    • Replies: 4
    • Views: 144
    15th March 2017, 19:59 Go to last post
  3. newbie's questions about PAL

    Started by dk_spb, 24th February 2017 16:40
    • Replies: 18
    • Views: 398
    15th March 2017, 10:51 Go to last post
    • Replies: 9
    • Views: 301
    FvM
    15th March 2017, 10:35 Go to last post
    • Replies: 4
    • Views: 310
    15th March 2017, 10:26 Go to last post
  4. [SOLVED] Verilog counter not counting

    Started by DocJava, 14th March 2017 14:32
    • Replies: 4
    • Views: 242
    14th March 2017, 16:29 Go to last post
  5. Round Robin systemverilog code question

    Started by promach, 14th March 2017 14:45
    • Replies: 1
    • Views: 227
    14th March 2017, 16:10 Go to last post
  6. Failing Timequest path not shown in RTL viewer

    Started by shaiko, 9th March 2017 09:49
    • Replies: 4
    • Views: 236
    13th March 2017, 21:00 Go to last post
  7. FPGA Prototyping of ZSP DSP 900

    Started by velu.plg, 10th March 2017 11:27
    • Replies: 5
    • Views: 229
    13th March 2017, 17:01 Go to last post
  8. VHDL code exercise. Please help!!

    Started by robertocastiglioni, 13th March 2017 01:09
    • Replies: 5
    • Views: 304
    13th March 2017, 16:30 Go to last post
  9. [SOLVED] SPI EEPROM and GPS Receiver

    Started by rayhh27, 10th March 2017 09:33
    • Replies: 1
    • Views: 226
    10th March 2017, 15:52 Go to last post
  10. Native VHDL negation function

    Started by shaiko, 8th March 2017 11:30
    • Replies: 8
    • Views: 241
    9th March 2017, 22:43 Go to last post
  11. how to call decimal values in verilog

    Started by emerson_11, 7th March 2017 10:17
    • Replies: 7
    • Views: 280
    9th March 2017, 18:08 Go to last post
  12. VHDL process fundamentals

    Started by Ripatti, 9th March 2017 12:51
    • Replies: 1
    • Views: 189
    9th March 2017, 13:14 Go to last post
  13. microblaze c code help

    Started by linuscomex, 9th March 2017 11:31
    • Replies: 0
    • Views: 180
    9th March 2017, 11:31 Go to last post
  14. when the "signal will update" in fpga

    Started by chandru4u4, 9th March 2017 05:08
    • Replies: 4
    • Views: 228
    9th March 2017, 10:17 Go to last post
  15. [SOLVED] Mul18x18 Xilinx primitive + modelsim simu

    Started by flote21, 8th March 2017 18:33
    • Replies: 2
    • Views: 242
    9th March 2017, 07:43 Go to last post
  16. FMC104 and VCU118 Compatibility

    Started by sahar8j, 8th March 2017 12:02
    • Replies: 2
    • Views: 145
    9th March 2017, 06:51 Go to last post
    • Replies: 3
    • Views: 314
    8th March 2017, 17:24 Go to last post
  17. module instantiation

    Started by ecasha, 8th March 2017 06:05
    • Replies: 4
    • Views: 243
    8th March 2017, 16:49 Go to last post
  18. The error about ARAM reading

    Started by Kynix, 7th March 2017 08:00
    • Replies: 3
    • Views: 243
    8th March 2017, 02:40 Go to last post
  19. s27 Benchmark circuit

    Started by ecasha, 7th March 2017 14:12
    • Replies: 1
    • Views: 155
    7th March 2017, 15:06 Go to last post
  20. Xilinx AXI GPIO IP core

    Started by beginner_EDA, 6th March 2017 14:51
    • Replies: 2
    • Views: 248
    7th March 2017, 08:07 Go to last post
  21. Video DAC ADV7123 related

    Started by garimella, 22nd February 2017 07:51
    • Replies: 12
    • Views: 376
    6th March 2017, 16:27 Go to last post
  22. VHDL SINE LUT using type "real"

    Started by shaiko, 5th March 2017 18:24
    • Replies: 2
    • Views: 221
    FvM
    6th March 2017, 08:02 Go to last post
  23. The performance metric for FPGAs

    Started by sai_shashi, 4th March 2017 02:51
    • Replies: 1
    • Views: 172
    4th March 2017, 11:05 Go to last post
    • Replies: 1
    • Views: 190
    4th March 2017, 07:01 Go to last post

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