Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2552052
date_generatedSun Jun 13 12:34:32 2021 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_ide7e9fd8e0cd6476983878df13334be68
project_iteration1 random_id126d164da418523181d4ebd2fc2f49da
registration_id212004825_0_0_500 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Phenom(tm) II X4 955 Processor cpu_speed3214 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
addresstreetablepanel_address_tree_table=2 applyrsbmultiautomationdialog_checkbox_tree=3 basedialog_apply=1 basedialog_cancel=4
basedialog_ok=23 boardchooser_board_table=1 cmdmsgdialog_ok=3 commonoptionschooserpanel_specify_generics_parameters=1
constraintschooserpanel_create_file=1 coretreetablepanel_core_tree_table=12 createconstraintsfilepanel_file_name=1 createnewdiagramdialog_design_name=1
filesetpanel_file_set_panel_tree=16 flownavigatortreepanel_flow_navigator_tree=3 gettingstartedview_create_new_project=1 hpopuptitle_close=1
mainmenumgr_window=2 microblaze_wizard_general_settings_enable_discrete_ports=2 microblaze_wizard_general_settings_use_exceptions=2 microblaze_wizard_general_settings_use_instruction_and_data_caches=1
pacommandnames_add_sources=1 pacommandnames_auto_update_hier=1 pacommandnames_create_top_hdl=1 pacommandnames_customize_rsb_bloc=10
pacommandnames_generate_composite_file=1 pacommandnames_project_summary=1 pacommandnames_regenerate_layout=4 pacommandnames_run_bitgen=1
pacommandnames_save_rsb_design=5 pacommandnames_validate_rsb_design=5 pacommandnames_zoom_in=2 pacommandnames_zoom_out=2
paviews_project_summary=1 paviews_system=2 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1
rdicommands_delete=2 rdicommands_properties=1 rdicommands_save_file=2 rsbapplyautomationbar_run_block_automation=1
rsbapplyautomationbar_run_connection_automation=5 selectmenu_highlight=7 settingsprojectgeneralpage_target_language=1 simpleoutputproductdialog_generate_output_products_immediately=1
srcmenu_ip_hierarchy=1 systembuildermenu_add_ip=2 systembuildermenu_ip_documentation=22 systembuilderview_expand_collapse=48
systembuilderview_orientation=29 systembuilderview_pinning=37 xpg_textfield_value_of_specified_parameter=1
java_command_handlers
addsources=1 createblockdesign=1 createtophdl=1 customizersbblock=11
editdelete=2 editproperties=1 managecompositetargets=1 newproject=1
projectsummary=1 regeneratersblayout=4 runbitgen=1 runimplementation=1
runsynthesis=1 saversbdesign=5 toolssettings=1 validatersbdesign=5
zoomin=2 zoomout=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=14 totalsynthesisruns=14

unisim_transformation
post_unisim_transformation
and2b1l=1 bscane2=1 bufg=2 bufgctrl=1
bufh=1 carry4=87 fdce=286 fdpe=7
fdre=2492 fdse=100 gnd=437 ibuf=3
lut1=36 lut2=209 lut3=516 lut4=520
lut5=652 lut6=821 mmcme2_adv=1 muxf7=112
obuf=1 ramb36e1=2 ramd32=160 rams32=32
srl16e=133 srlc16e=96 srlc32e=1 vcc=226
pre_unisim_transformation
and2b1l=1 bscane2=1 bufg=2 bufgctrl=1
bufh=1 carry4=87 fdce=286 fdpe=7
fdre=2492 fdse=100 gnd=437 ibuf=3
lut1=36 lut2=209 lut3=516 lut4=520
lut5=588 lut6=757 lut6_2=64 mmcme2_adv=1
muxf7=112 obuf=1 ram32m=16 ram32x1d=32
ramb36e1=2 srl16e=133 srlc16e=96 srlc32e=1
vcc=226

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=4 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2071 srls_augmented=0
srls_newly_gated=0 srls_total=224

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=5 da_board_cnt=6
da_mb_cnt=1 iptotal=1 maxhierdepth=1 numblks=23
numhdlrefblks=0 numhierblks=9 numhlsblks=0 numnonxlnxblks=0
numpkgbdblks=0 numreposblks=14 numsysgenblks=0 synth_mode=OOC_per_IP
x_iplanguage=VHDL x_iplibrary=BlockDiagram x_ipname=uBlaze_1 x_ipvendor=xilinx.com
x_ipversion=1.00.a
MDM/1
c_addr_size=32 c_avoid_primitives=0 c_bscanid=76547328 c_data_size=32
c_dbg_mem_access=0 c_dbg_reg_access=0 c_debug_interface=0 c_ext_trig_reset_value=0xF1234
c_family=artix7 c_interconnect=2 c_jtag_chain=2 c_m_axi_addr_width=32
c_m_axi_data_width=32 c_m_axi_thread_id_width=1 c_m_axis_data_width=32 c_m_axis_id_width=7
c_mb_dbg_ports=1 c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32
c_trace_async_reset=0 c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_trace_data_width=32
c_trace_id=110 c_trace_output=0 c_trace_protocol=1 c_use_bscan=0
c_use_config_reset=0 c_use_cross_trigger=0 c_use_uart=1 core_container=NA
iptotal=1 x_ipcorerevision=16 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=mdm x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=0 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=8192 c_d_axi=1 c_d_lmb=1
c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=0 c_dcache_always_used=0
c_dcache_baseaddr=0x0000000000000000 c_dcache_byte_size=8192 c_dcache_data_width=0 c_dcache_force_tag_lutram=1
c_dcache_highaddr=0x000000003fffffff c_dcache_line_len=4 c_dcache_use_writeback=1 c_dcache_victims=2
c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5 c_debug_external_trace=0
c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0 c_debug_trace_async_reset=0
c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0 c_ecc_use_ce_exception=0
c_edge_is_positive=1 c_endianness=1 c_family=artix7 c_fault_tolerant=0
c_fpu_exception=0 c_freq=100000000 c_fsl_exception=0 c_fsl_links=2
c_i_axi=1 c_i_lmb=1 c_iaddr_size=32 c_icache_always_used=1
c_icache_baseaddr=0x0000000000000000 c_icache_data_width=0 c_icache_force_tag_lutram=1 c_icache_highaddr=0x000000003fffffff
c_icache_line_len=4 c_icache_streams=1 c_icache_victims=2 c_ill_opcode_exception=0
c_imprecise_exceptions=0 c_instance=uBlaze_1_microblaze_0_0 c_instr_size=32 c_interconnect=2
c_interrupt_is_edge=0 c_lmb_data_size=32 c_lockstep_master=0 c_lockstep_slave=0
c_m0_axis_data_width=32 c_m10_axis_data_width=32 c_m11_axis_data_width=32 c_m12_axis_data_width=32
c_m13_axis_data_width=32 c_m14_axis_data_width=32 c_m15_axis_data_width=32 c_m1_axis_data_width=32
c_m2_axis_data_width=32 c_m3_axis_data_width=32 c_m4_axis_data_width=32 c_m5_axis_data_width=32
c_m6_axis_data_width=32 c_m7_axis_data_width=32 c_m8_axis_data_width=32 c_m9_axis_data_width=32
c_m_axi_d_bus_exception=0 c_m_axi_dc_addr_width=32 c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5
c_m_axi_dc_buser_width=1 c_m_axi_dc_data_width=32 c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1
c_m_axi_dc_thread_id_width=1 c_m_axi_dc_user_value=31 c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32
c_m_axi_dp_data_width=32 c_m_axi_dp_exclusive_access=0 c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0
c_m_axi_ic_addr_width=32 c_m_axi_ic_aruser_width=5 c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1
c_m_axi_ic_data_width=32 c_m_axi_ic_ruser_width=1 c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31
c_m_axi_ic_wuser_width=1 c_m_axi_ip_addr_width=32 c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1
c_mmu_dtlb_size=4 c_mmu_itlb_size=2 c_mmu_privileged_instr=0 c_mmu_tlb_access=3
c_mmu_zones=16 c_num_sync_ff_clk=2 c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1
c_num_sync_ff_dbg_clk=1 c_num_sync_ff_dbg_trace_clk=2 c_number_of_pc_brk=4 c_number_of_rd_addr_brk=2
c_number_of_wr_addr_brk=2 c_opcode_0x0_illegal=0 c_optimization=0 c_pc_width=32
c_piaddr_size=32 c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000
c_reset_msr=0x00000000 c_s0_axis_data_width=32 c_s10_axis_data_width=32 c_s11_axis_data_width=32
c_s12_axis_data_width=32 c_s13_axis_data_width=32 c_s14_axis_data_width=32 c_s15_axis_data_width=32
c_s1_axis_data_width=32 c_s2_axis_data_width=32 c_s3_axis_data_width=32 c_s4_axis_data_width=32
c_s5_axis_data_width=32 c_s6_axis_data_width=32 c_s7_axis_data_width=32 c_s8_axis_data_width=32
c_s9_axis_data_width=32 c_sco=0 c_unaligned_exceptions=0 c_use_barrel=1
c_use_branch_target_cache=0 c_use_config_reset=0 c_use_dcache=0 c_use_div=1
c_use_ext_brk=0 c_use_ext_nm_brk=0 c_use_extended_fsl_instr=0 c_use_fpu=0
c_use_hw_mul=0 c_use_icache=0 c_use_interrupt=2 c_use_mmu=0
c_use_msr_instr=1 c_use_non_secure=0 c_use_pcmp_instr=1 c_use_reorder_instr=1
c_use_stack_protection=0 core_container=NA iptotal=1 x_ipcorerevision=1
x_iplanguage=VHDL x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=11.0
axi_crossbar_v2_1_20_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=artix7
c_m_axi_addr_width=0x0000000f0000000c00000010 c_m_axi_base_addr=0x000000004060000000000000414000000000000041200000 c_m_axi_read_connectivity=0x0000000f0000000f0000000f c_m_axi_read_issuing=0x000000010000000100000001
c_m_axi_secure=0x000000000000000000000000 c_m_axi_write_connectivity=0x0000000d0000000d0000000d c_m_axi_write_issuing=0x000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=3 c_num_slave_slots=4 c_r_register=1 c_s_axi_arb_priority=0x00000000000000000000000000000000
c_s_axi_base_id=0x00000003000000020000000100000000 c_s_axi_read_acceptance=0x00000001000000010000000100000001 c_s_axi_single_thread=0x00000001000000010000000100000001 c_s_axi_thread_id_width=0x00000000000000000000000000000000
c_s_axi_write_acceptance=0x00000001000000010000000100000001 core_container=NA iptotal=1 x_ipcorerevision=20
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_intc/1
c_addr_width=32 c_async_intr=0xFFFFFFFE c_cascade_master=0 c_disable_synchronizers=1
c_en_cascade_mode=0 c_enable_async=0 c_family=artix7 c_has_cie=1
c_has_fast=1 c_has_ilr=0 c_has_ipr=1 c_has_ivr=1
c_has_sie=1 c_instance=uBlaze_1_microblaze_0_axi_intc_0 c_irq_active=0x1 c_irq_is_level=1
c_ivar_reset_value=0x0000000000000010 c_kind_of_edge=0xFFFFFFFF c_kind_of_intr=0xFFFFFFFF c_kind_of_lvl=0xFFFFFFFF
c_mb_clk_not_connected=1 c_num_intr_inputs=2 c_num_sw_intr=0 c_num_sync_ff=2
c_s_axi_addr_width=9 c_s_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=13 x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_intc
x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_uartlite/1
c_baudrate=9600 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=23 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_3/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=2 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=1
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 10.7492 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=uBlaze_1_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=2048 c_read_depth_b=2048 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=32 c_read_width_b=32 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=1
c_use_byte_wea=1 c_use_byte_web=1 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=4 c_web_width=4
c_write_depth_a=2048 c_write_depth_b=2048 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=32 c_write_width_b=32 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=3 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v6_0_3_0_0/1
clkin1_period=83.333 clkin2_period=10.0 clock_mgr_type=NA component_name=uBlaze_1_clk_wiz_1_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=true num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000001FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_mask=0x0000000040000000 c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2 core_container=NA
iptotal=2 x_ipcorerevision=16 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=4.0
lmb_v10/1
c_ext_reset_high=1 c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_num_slaves=1
core_container=NA iptotal=2 x_ipcorerevision=9 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=lmb_v10 x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=3.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=1 c_ext_rst_width=4
c_family=artix7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VHDL x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
util_vector_logic_v2_0_1_util_vector_logic/1
c_operation=not c_size=1 core_container=NA iptotal=1
x_ipcorerevision=1 x_iplanguage=VHDL x_iplibrary=ip x_ipname=util_vector_logic
x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.0
xlconcat_v2_1_3_xlconcat/1
core_container=NA dout_width=2 in0_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in1_width=1 in20_width=1 in21_width=1
in22_width=1 in23_width=1 in24_width=1 in25_width=1
in26_width=1 in27_width=1 in28_width=1 in29_width=1
in2_width=1 in30_width=1 in31_width=1 in3_width=1
in4_width=1 in5_width=1 in6_width=1 in7_width=1
in8_width=1 in9_width=1 iptotal=1 num_ports=2
x_ipcorerevision=3 x_iplanguage=VHDL x_iplibrary=ip x_ipname=xlconcat
x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=1 bufhce_util_percentage=1.39
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=2 block_ram_tile_util_percentage=4.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=2 ramb36_fifo_util_percentage=4.00
ramb36e1_only_used=2
primitives
and2b1l_functional_category=Others and2b1l_used=1 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=2 bufgctrl_functional_category=Clock bufgctrl_used=1
bufh_functional_category=Clock bufh_used=1 carry4_functional_category=CarryLogic carry4_used=87
fdce_functional_category=Flop & Latch fdce_used=281 fdpe_functional_category=Flop & Latch fdpe_used=6
fdre_functional_category=Flop & Latch fdre_used=1686 fdse_functional_category=Flop & Latch fdse_used=98
ibuf_functional_category=IO ibuf_used=3 lut1_functional_category=LUT lut1_used=18
lut2_functional_category=LUT lut2_used=259 lut3_functional_category=LUT lut3_used=521
lut4_functional_category=LUT lut4_used=427 lut5_functional_category=LUT lut5_used=550
lut6_functional_category=LUT lut6_used=717 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=95 obuf_functional_category=IO obuf_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=2 ramd32_functional_category=Distributed Memory ramd32_used=160
rams32_functional_category=Distributed Memory rams32_used=32 srl16e_functional_category=Distributed Memory srl16e_used=135
srlc16e_functional_category=Distributed Memory srlc16e_used=88 srlc32e_functional_category=Distributed Memory srlc32e_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=95 f7_muxes_util_percentage=0.58
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=96 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2125 lut_as_logic_util_percentage=10.22 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=276 lut_as_memory_util_percentage=2.88 lut_as_shift_register_fixed=0 lut_as_shift_register_used=180
register_as_and_or_available=41600 register_as_and_or_fixed=0 register_as_and_or_used=1 register_as_and_or_util_percentage=<0.01
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=2071 register_as_flip_flop_util_percentage=4.98
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=2401 slice_luts_util_percentage=11.54
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=2072 slice_registers_util_percentage=4.98
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=96 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2125 lut_as_logic_util_percentage=10.22 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=276 lut_as_memory_util_percentage=2.88 lut_as_shift_register_fixed=0 lut_as_shift_register_used=180
lut_in_front_of_the_register_is_unused_fixed=180 lut_in_front_of_the_register_is_unused_used=534 lut_in_front_of_the_register_is_used_fixed=534 lut_in_front_of_the_register_is_used_used=430
register_driven_from_outside_the_slice_fixed=430 register_driven_from_outside_the_slice_used=964 register_driven_from_within_the_slice_fixed=964 register_driven_from_within_the_slice_used=1108
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=2072 slice_registers_util_percentage=4.98 slice_used=846 slice_util_percentage=10.38
slicel_fixed=0 slicel_used=580 slicem_fixed=0 slicem_used=266
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=105 unique_control_sets_util_percentage=1.29
using_o5_and_o6_fixed=1.29 using_o5_and_o6_used=44 using_o5_output_only_fixed=44 using_o5_output_only_used=15
using_o6_output_only_fixed=15 using_o6_output_only_used=121
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=uBlaze_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:51s hls_ip=0 memory_gain=584.996MB memory_peak=959.059MB