| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001 |
203 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb|adder |
12 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb |
7 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux |
303 |
0 |
0 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_002 |
103 |
1 |
2 |
1 |
101 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_001 |
104 |
4 |
2 |
4 |
201 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux |
104 |
4 |
2 |
4 |
201 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002 |
103 |
0 |
2 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001 |
203 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux |
203 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux_001 |
104 |
4 |
2 |
4 |
201 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux |
105 |
9 |
2 |
9 |
301 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004|the_default_decode |
0 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004 |
100 |
0 |
2 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003|the_default_decode |
0 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003 |
100 |
0 |
2 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002|the_default_decode |
0 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002 |
100 |
0 |
2 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001 |
100 |
0 |
4 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router |
100 |
0 |
4 |
0 |
101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_0_s1_agent_rsp_fifo |
140 |
39 |
0 |
39 |
99 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_0_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_0_s1_agent |
276 |
39 |
40 |
39 |
296 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
140 |
39 |
0 |
39 |
99 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent |
276 |
39 |
40 |
39 |
296 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_debug_mem_slave_agent_rsp_fifo |
140 |
39 |
0 |
39 |
99 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_debug_mem_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_debug_mem_slave_agent |
276 |
39 |
40 |
39 |
296 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_instruction_master_agent |
166 |
35 |
69 |
35 |
132 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_data_master_agent |
166 |
35 |
69 |
35 |
132 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_0_s1_translator |
87 |
22 |
36 |
22 |
57 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_translator |
103 |
7 |
4 |
7 |
89 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_debug_mem_slave_translator |
103 |
5 |
11 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_instruction_master_translator |
104 |
51 |
0 |
51 |
96 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen21_data_master_translator |
104 |
12 |
0 |
12 |
96 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0 |
163 |
0 |
0 |
0 |
192 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart_0|the_uart_qsys1_uart_0_regs |
41 |
9 |
6 |
9 |
40 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|uart_0|the_uart_qsys1_uart_0_rx|the_uart_qsys1_uart_0_rx_stimulus_source |
14 |
0 |
13 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart_0|the_uart_qsys1_uart_0_rx |
16 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|uart_0|the_uart_qsys1_uart_0_tx |
24 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart_0 |
26 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0|the_altsyncram|auto_generated|mux2 |
227 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0|the_altsyncram|auto_generated|decode3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0|the_altsyncram|auto_generated |
55 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0 |
58 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_debug_slave_wrapper|the_uart_qsys1_nios2_gen21_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_debug_slave_wrapper|the_uart_qsys1_nios2_gen21_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_ocimem|uart_qsys1_nios2_gen21_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_ocimem|uart_qsys1_nios2_gen21_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_avalon_reg |
48 |
0 |
29 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_dtrace|uart_qsys1_nios2_gen21_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_dtrace |
105 |
0 |
94 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_itrace |
24 |
54 |
24 |
54 |
54 |
54 |
54 |
54 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_dbrk |
90 |
0 |
0 |
0 |
94 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_xbrk |
56 |
5 |
53 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci|the_uart_qsys1_nios2_gen21_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_nios2_oci |
160 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|uart_qsys1_nios2_gen21_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|uart_qsys1_nios2_gen21_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|uart_qsys1_nios2_gen21_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|uart_qsys1_nios2_gen21_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu|the_uart_qsys1_nios2_gen21_cpu_test_bench |
294 |
3 |
260 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21|cpu |
149 |
1 |
31 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen21 |
149 |
0 |
0 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0 |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |