matrix_multiplication Project Status (07/10/2019 - 11:53:00)
Project File: Matrix4DimMultiplyVerilog.xise Parser Errors: No Errors
Module Name: matrix_multiplication Implementation State: Translated (Failed)
Target Device: xc6slx9-3tqg144
  • Errors:
X 3 Errors (3 new)
Product Version:ISE 14.7
  • Warnings:
41 Warnings (40 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 10 11440 0%
Number of Slice LUTs 11 5720 0%
Number of fully used LUT-FF pairs 10 11 90%
Number of bonded IOBs 18 102 17%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentœr. 10. lip 11:52:55 2019041 Warnings (40 new)96 Infos (96 new)
Translation ReportCurrentœr. 10. lip 11:52:59 2019X 3 Errors (3 new)00
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 07/10/2019 - 11:53:00