matrix_multiplication Project Status (07/10/2019 - 09:34:41)
Project File: Matrix4DimMultiplyVerilog.xise Parser Errors: No Errors
Module Name: ROM Implementation State: Synthesized (Failed)
Target Device: xc6slx9-3tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentœr. 10. lip 09:28:40 2019   
Translation ReportCurrentœr. 10. lip 09:28:44 201901 Warning (0 new)0
Map ReportCurrentœr. 10. lip 09:28:47 2019X 2 Errors (0 new)00
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 07/10/2019 - 09:34:41