matrix_multiplication Project Status (07/10/2019 - 11:53:00) | |||
Project File: | Matrix4DimMultiplyVerilog.xise | Parser Errors: | No Errors |
Module Name: | matrix_multiplication | Implementation State: | Translated (Failed) |
Target Device: | xc6slx9-3tqg144 |
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X 3 Errors (3 new) |
Product Version: | ISE 14.7 |
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41 Warnings (40 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 10 | 11440 | 0% | |
Number of Slice LUTs | 11 | 5720 | 0% | |
Number of fully used LUT-FF pairs | 10 | 11 | 90% | |
Number of bonded IOBs | 18 | 102 | 17% | |
Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | œr. 10. lip 11:52:55 2019 | 0 | 41 Warnings (40 new) | 96 Infos (96 new) | |
Translation Report | Current | œr. 10. lip 11:52:59 2019 | X 3 Errors (3 new) | 0 | 0 | |
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |