matrix_multiplication Project Status (07/10/2019 - 11:37:54) | |||
Project File: | Matrix4DimMultiplyVerilog.xise | Parser Errors: | No Errors |
Module Name: | Matrix_A | Implementation State: | Translated (Failed) |
Target Device: | xc6slx9-3tqg144 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | œr. 10. lip 10:45:29 2019 | ||||
Translation Report | Current | œr. 10. lip 10:45:32 2019 | ||||
Map Report | Current | œr. 10. lip 10:45:35 2019 | X 2 Errors (0 new) | 0 | 0 | |
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |