Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedThu Jun 3 10:59:03 2021 os_platformWIN64
product_versionVivado v2020.1 (64-bit) project_id20f36b9dbdf447b88be81a20aa83c676
project_iteration7 random_ida32790a03520543595693428a9eadc33
registration_id212004825_0_0_500 route_designTRUE
target_devicexc7s15 target_familyspartan7
target_packageftgb196 target_speed-2
tool_flowVivado

user_environment
cpu_nameAMD Phenom(tm) II X4 955 Processor cpu_speed3214 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_add_element=1 abstractfileview_close=1 abstractfileview_reload=1 addsrcwizard_specify_hdl_netlist_block_design=1
basedialog_apply=1 basedialog_cancel=3 basedialog_ok=131 cmdmsgdialog_ok=7
constraintschooserpanel_add_existing_or_create_new_constraints=1 constraintschooserpanel_create_file=1 coretreetablepanel_core_tree_table=22 createconstraintsfilepanel_file_name=1
createsrcfiledialog_file_name=1 definemodulesdialog_architecture_name=1 definemodulesdialog_define_modules_and_specify_io_ports=10 filesetpanel_file_set_panel_tree=97
flownavigatortreepanel_flow_navigator_tree=33 fpgachooser_family=1 fpgachooser_fpga_table=1 gettingstartedview_create_new_project=1
graphicalview_select=1 hardwaretreepanel_hardware_tree_table=7 hcodeeditor_blank_operations=9 hcodeeditor_commands_to_fold_text=7
hcodeeditor_diff_with=7 hcodeeditor_search_text_combo_box=1 hinputhandler_indent_selection=1 hinputhandler_toggle_line_comments=1
mainmenumgr_checkpoint=5 mainmenumgr_export=2 mainmenumgr_file=8 mainmenumgr_flow=2
mainmenumgr_ip=5 mainmenumgr_project=4 mainmenumgr_reports=4 mainmenumgr_settings=1
mainmenumgr_text_editor=5 mainmenumgr_tools=4 mainmenumgr_unselect_type=2 mainmenumgr_view=4
mainmenumgr_window=4 mainwinmenumgr_layout=2 msgtreepanel_message_view_tree=6 msgview_critical_warnings=1
msgview_error_messages=2 netlistschematicview_show_io_ports_in_this_schematic=1 netlistschematicview_show_nets_in_this_schematic=1 pacommandnames_add_sources=5
pacommandnames_auto_connect_target=5 pacommandnames_auto_update_hier=11 pacommandnames_close_project=3 pacommandnames_impl_settings=1
pacommandnames_open_hardware_manager=5 pacommandnames_reports_window=1 pacommandnames_run_bitgen=9 pacommandnames_schematic=4
pacommandnames_select_area=1 pacommandnames_simulation_run=1 pacommandnames_zoom_in=7 paviews_code=7
paviews_device=1 paviews_ip_catalog=1 paviews_project_summary=6 paviews_schematic=4
programdebugtab_open_target=5 programdebugtab_program_device=7 programfpgadialog_program=7 programfpgadialog_specify_bitstream_file=6
projectnamechooser_project_name=1 rdicommands_custom_commands=6 rdicommands_save_file=49 rungadget_show_error=1
rungadget_show_error_and_critical_warning_messages=2 rungadget_show_warning_and_error_messages_in_messages=5 saveprojectutils_save=1 settingsdialog_project_tree=1
signaltreepanel_signal_tree_table=7 simpleoutputproductdialog_generate_output_products_immediately=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 srcchooserpanel_create_file=1
srcmenu_ip_documentation=2 srcmenu_ip_hierarchy=11 srcmenu_refresh_hierarchy=4 statemonitor_reset_run=1
syntheticagettingstartedview_recent_projects=3 syntheticastatemonitor_cancel=4 taskbanner_close=7
java_command_handlers
addsources=5 autoconnecttarget=5 closeproject=3 coreview=1
customizecore=1 launchprogramfpga=7 newproject=1 openhardwaremanager=5
recustomizecore=1 runbitgen=9 runimplementation=20 runschematic=4
runsynthesis=27 showview=22 toggleselectareamode=1 toolssettings=1
viewtaskimplementation=1 viewtaskrtlanalysis=1 zoomin=7
other_data
guimode=4
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=1 bufgctrl=1 bufh=1 carry4=61
fdce=106 fdpe=5 fdre=330 fdse=1
gnd=5 ibuf=25 lut1=39 lut2=130
lut3=95 lut4=61 lut5=238 lut6=283
obuf=29 obuft=16 plle2_adv=1 ramb18e1=1
ramd32=84 rams32=28 vcc=4
pre_unisim_transformation
bufg=1 bufgctrl=1 bufh=1 carry4=61
fdce=106 fdpe=5 fdre=330 fdse=1
gnd=5 ibuf=9 iobuf=16 lut1=39
lut2=130 lut3=95 lut4=61 lut5=238
lut6=283 obuf=29 plle2_adv=1 ram32m=14
ramb18e1=1 vcc=4

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=442 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_5_0_0/1
clkin1_period=20.000 clkin2_period=10.000 clock_mgr_type=NA component_name=clk_wiz_1
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-7=1

report_utilization
clocking
bufgctrl_available=16 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=12.50
bufhce_available=24 bufhce_fixed=0 bufhce_used=1 bufhce_util_percentage=4.17
bufio_available=8 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=4 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=8 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=2 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=2 plle2_adv_fixed=0 plle2_adv_used=1 plle2_adv_util_percentage=50.00
dsp
dsps_available=20 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=10 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=5.00
ramb18_available=20 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=5.00
ramb18e1_only_used=1 ramb36_fifo_available=10 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 bufgctrl_functional_category=Clock bufgctrl_used=1
bufh_functional_category=Clock bufh_used=1 carry4_functional_category=CarryLogic carry4_used=61
fdce_functional_category=Flop & Latch fdce_used=106 fdpe_functional_category=Flop & Latch fdpe_used=5
fdre_functional_category=Flop & Latch fdre_used=330 fdse_functional_category=Flop & Latch fdse_used=1
ibuf_functional_category=IO ibuf_used=25 lut1_functional_category=LUT lut1_used=38
lut2_functional_category=LUT lut2_used=130 lut3_functional_category=LUT lut3_used=96
lut4_functional_category=LUT lut4_used=61 lut5_functional_category=LUT lut5_used=238
lut6_functional_category=LUT lut6_used=282 obuf_functional_category=IO obuf_used=29
obuft_functional_category=IO obuft_used=16 plle2_adv_functional_category=Clock plle2_adv_used=1
ramb18e1_functional_category=Block Memory ramb18e1_used=1 ramd32_functional_category=Distributed Memory ramd32_used=84
rams32_functional_category=Distributed Memory rams32_used=28
slice_logic
f7_muxes_available=4000 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=2000 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=56 lut_as_logic_available=8000 lut_as_logic_fixed=0
lut_as_logic_used=722 lut_as_logic_util_percentage=9.03 lut_as_memory_available=2400 lut_as_memory_fixed=0
lut_as_memory_used=56 lut_as_memory_util_percentage=2.33 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=16000 register_as_flip_flop_fixed=0 register_as_flip_flop_used=442 register_as_flip_flop_util_percentage=2.76
register_as_latch_available=16000 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=8000 slice_luts_fixed=0 slice_luts_used=778 slice_luts_util_percentage=9.73
slice_registers_available=16000 slice_registers_fixed=0 slice_registers_used=442 slice_registers_util_percentage=2.76
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=56 lut_as_logic_available=8000 lut_as_logic_fixed=0
lut_as_logic_used=722 lut_as_logic_util_percentage=9.03 lut_as_memory_available=2400 lut_as_memory_fixed=0
lut_as_memory_used=56 lut_as_memory_util_percentage=2.33 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=104 lut_in_front_of_the_register_is_used_fixed=104 lut_in_front_of_the_register_is_used_used=90
register_driven_from_outside_the_slice_fixed=90 register_driven_from_outside_the_slice_used=194 register_driven_from_within_the_slice_fixed=194 register_driven_from_within_the_slice_used=248
slice_available=2000 slice_fixed=0 slice_registers_available=16000 slice_registers_fixed=0
slice_registers_used=442 slice_registers_util_percentage=2.76 slice_used=270 slice_util_percentage=13.50
slicel_fixed=0 slicel_used=172 slicem_fixed=0 slicem_used=98
unique_control_sets_available=2000 unique_control_sets_fixed=2000 unique_control_sets_used=25 unique_control_sets_util_percentage=1.25
using_o5_and_o6_fixed=1.25 using_o5_and_o6_used=56 using_o5_output_only_fixed=56 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7s15ftgb196-2 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=Top_InstantSoC -verilog_define=default::[not_specified]
usage
elapsed=00:01:29s hls_ip=0 memory_gain=129.918MB memory_peak=1156.141MB