Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2552052
date_generatedSun Jul 4 13:00:33 2021 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_id56bf8d4d49664eb1b4baa4fcae8c7d09
project_iteration2 random_id9c5b461cd6a85be5a996f74d22cd175b
registration_id9c5b461cd6a85be5a996f74d22cd175b route_designTRUE
target_devicexc7s15 target_familyspartan7
target_packageftgb196 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-8750H CPU @ 2.20GHz cpu_speed2208 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_cancel=5 basedialog_ok=65 confirmsavetexteditsdialog_yes=1 filesetpanel_file_set_panel_tree=69
findandreplacealldialog_find=2 findinfilesview_replace_all_occurrences_in_all_files=2 floorplaneditor_metric=5 flownavigatortreepanel_flow_navigator_tree=13
fpgachooser_family=1 gettingstartedview_open_project=2 graphicalview_select=7 hcodeeditor_blank_operations=2
hcodeeditor_commands_to_fold_text=1 hcodeeditor_diff_with=2 hcodeeditor_search_text_combo_box=1 hinputhandler_toggle_line_comments=7
hpopuptitle_close=1 instancemenu_floorplanning=3 mainmenumgr_checkpoint=4 mainmenumgr_edit=4
mainmenumgr_export=1 mainmenumgr_file=10 mainmenumgr_ip=4 mainmenumgr_project=4
mainmenumgr_text_editor=3 mainmenumgr_view=2 mainmenumgr_window=4 mainwinmenumgr_layout=4
msgtreepanel_message_view_tree=8 msgview_information_messages=2 msgview_warning_messages=2 netlisttreeview_netlist_tree=14
numjobschooser_number_of_jobs=1 pacommandnames_auto_update_hier=7 pacommandnames_close_project=3 pacommandnames_generate_composite_file=1
pacommandnames_project_summary=1 pacommandnames_replace_in_files=2 pacommandnames_reports_window=2 pacommandnames_run_bitgen=4
pacommandnames_run_implementation=2 pacommandnames_schematic=3 pacommandnames_zoom_in=18 pagraphicalview_view=9
paviews_device=13 paviews_schematic=2 primitivesmenu_color=2 primitivesmenu_highlight_leaf_cells=5
projectsummarydrcpanel_open_drc_report=1 projecttab_close_design=1 rdicommands_save_file=17 rungadget_show_warning_and_error_messages_in_messages=1
selectmenu_highlight=8 selectmenu_mark=5 settingsprojectgeneralpage_choose_device_for_your_project=1 simpleoutputproductdialog_generate_output_products_immediately=6
srcmenu_ip_documentation=2 srcmenu_ip_hierarchy=11 srcmenu_refresh_hierarchy=1 stalemoreaction_out_of_date_details=1
syntheticagettingstartedview_recent_projects=3 taskbanner_close=4
java_command_handlers
closeproject=4 managecompositetargets=1 openexistingreport=1 openproject=2
projectsummary=1 recustomizecore=9 runbitgen=4 runimplementation=9
runschematic=3 runsynthesis=10 showview=6 toolssettings=3
ui.views.c.h.e=2 viewtaskimplementation=4 zoomin=20
other_data
guimode=6
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=8 export_simulation_ies=8
export_simulation_modelsim=8 export_simulation_questa=8 export_simulation_riviera=8 export_simulation_vcs=8
export_simulation_xsim=8 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=7 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=7 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bufg=2 carry4=125 fdpe=4 fdre=3222
fdse=132 gnd=112 ibuf=19 lut1=27
lut2=376 lut3=693 lut4=469 lut5=496
lut6=932 mmcme2_adv=1 muxf7=364 muxf8=182
obuf=42 obuft=16 ramb18e1=1 rams64e=464
srl16e=241 srlc32e=264 vcc=124
pre_unisim_transformation
bufg=2 carry4=125 fdpe=4 fdre=3222
fdse=132 gnd=112 ibuf=3 iobuf=16
lut1=27 lut2=376 lut3=693 lut4=469
lut5=496 lut6=932 mmcme2_adv=1 muxf7=132
muxf8=66 obuf=42 ram256x1s=116 ramb18e1=1
srl16e=241 srlc32e=264 vcc=124

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=3087 srls_augmented=0
srls_newly_gated=0 srls_total=449

ip_statistics
axi_bram_ctrl/1
c_bram_addr_width=10 c_bram_inst_mode=EXTERNAL c_ecc=0 c_ecc_onoff_reset_value=0
c_ecc_type=0 c_family=spartan7 c_fault_inject=0 c_memory_depth=1024
c_rd_cmd_optimization=0 c_read_latency=1 c_s_axi_addr_width=12 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4
c_s_axi_supports_narrow_burst=0 c_single_port_bram=1 core_container=NA iptotal=1
x_ipcorerevision=1 x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_bram_ctrl
x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_cdma/1
c_axi_lite_is_async=0 c_dlytmr_resolution=256 c_family=spartan7 c_include_dre=1
c_include_sf=0 c_include_sg=0 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_max_burst_len=16 c_m_axi_sg_addr_width=32 c_m_axi_sg_data_width=32 c_read_addr_pipe_depth=4
c_s_axi_lite_addr_width=6 c_s_axi_lite_data_width=32 c_use_datamover_lite=0 c_write_addr_pipe_depth=4
core_container=NA iptotal=2 x_ipcorerevision=19 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=axi_cdma x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.1
axi_emc/1
c_axi_clk_period_ps=10000 c_family=spartan7 c_include_datawidth_matching_0=1 c_include_datawidth_matching_1=1
c_include_datawidth_matching_2=1 c_include_datawidth_matching_3=1 c_include_negedge_ioregs=0 c_instance=axi_emc_inst
c_lflash_period_ps=10000 c_linear_flash_sync_burst=0 c_max_mem_width=16 c_mem0_type=1
c_mem0_width=16 c_mem1_type=0 c_mem1_width=16 c_mem2_type=0
c_mem2_width=16 c_mem3_type=0 c_mem3_width=16 c_mem_a_lsb=0
c_mem_a_msb=31 c_num_banks_mem=1 c_page_size=16 c_parity_type_mem_0=0
c_parity_type_mem_1=0 c_parity_type_mem_2=0 c_parity_type_mem_3=0 c_port_diff=0
c_s_axi_en_reg=0 c_s_axi_mem0_baseaddr=0x60000000 c_s_axi_mem0_highaddr=0x61FFFFFF c_s_axi_mem1_baseaddr=0xB0000000
c_s_axi_mem1_highaddr=0xBFFFFFFF c_s_axi_mem2_baseaddr=0xC0000000 c_s_axi_mem2_highaddr=0xCFFFFFFF c_s_axi_mem3_baseaddr=0xD0000000
c_s_axi_mem3_highaddr=0xDFFFFFFF c_s_axi_mem_addr_width=32 c_s_axi_mem_data_width=32 c_s_axi_mem_id_width=1
c_s_axi_reg_addr_width=5 c_s_axi_reg_data_width=32 c_synch_pipedelay_0=1 c_synch_pipedelay_1=1
c_synch_pipedelay_2=1 c_synch_pipedelay_3=1 c_tavdv_ps_mem_0=12000 c_tavdv_ps_mem_1=15000
c_tavdv_ps_mem_2=15000 c_tavdv_ps_mem_3=15000 c_tcedv_ps_mem_0=12000 c_tcedv_ps_mem_1=15000
c_tcedv_ps_mem_2=15000 c_tcedv_ps_mem_3=15000 c_thzce_ps_mem_0=6000 c_thzce_ps_mem_1=7000
c_thzce_ps_mem_2=7000 c_thzce_ps_mem_3=7000 c_thzoe_ps_mem_0=6000 c_thzoe_ps_mem_1=7000
c_thzoe_ps_mem_2=7000 c_thzoe_ps_mem_3=7000 c_tlzwe_ps_mem_0=3000 c_tlzwe_ps_mem_1=0
c_tlzwe_ps_mem_2=0 c_tlzwe_ps_mem_3=0 c_tpacc_ps_flash_0=25000 c_tpacc_ps_flash_1=25000
c_tpacc_ps_flash_2=25000 c_tpacc_ps_flash_3=25000 c_twc_ps_mem_0=12000 c_twc_ps_mem_1=15000
c_twc_ps_mem_2=15000 c_twc_ps_mem_3=15000 c_twp_ps_mem_0=8000 c_twp_ps_mem_1=12000
c_twp_ps_mem_2=12000 c_twp_ps_mem_3=12000 c_twph_ps_mem_0=12000 c_twph_ps_mem_1=12000
c_twph_ps_mem_2=12000 c_twph_ps_mem_3=12000 c_use_startup=0 c_wr_rec_time_mem_0=27000
c_wr_rec_time_mem_1=27000 c_wr_rec_time_mem_2=27000 c_wr_rec_time_mem_3=27000 core_container=NA
iptotal=1 x_ipcorerevision=19 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_emc x_ipproduct=Vivado 2019.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=3.0
axi_traffic_gen_v3_0_5_top/1
c_atg_axis_data_gen_type=0 c_atg_basic_axi4=0 c_atg_hltp_mode=0 c_atg_mif_addr_bits=8
c_atg_mif_data_depth=256 c_atg_repeat_type=0 c_atg_slave_only=0 c_atg_static=0
c_atg_static_en_read=1 c_atg_static_en_write=1 c_atg_static_free_run=1 c_atg_static_incr=0
c_atg_static_length=16 c_atg_static_rd_address=0x0000000013A00000 c_atg_static_rd_high_address=0x0000000013A00FFF c_atg_static_rd_pipeline=3
c_atg_static_trangap=0 c_atg_static_wr_address=0x0000000012A00000 c_atg_static_wr_high_address=0x0000000012A00FFF c_atg_static_wr_pipeline=3
c_atg_streaming=0 c_atg_streaming_max_len_bits=16 c_atg_streaming_mem_file=no_mem_file_loaded c_atg_streaming_mst_lpbk=0
c_atg_streaming_mst_only=1 c_atg_streaming_slv_lpbk=0 c_atg_system_ch1_high=0x00001FFF c_atg_system_ch1_low=0x00001000
c_atg_system_ch2_high=0x00002FFF c_atg_system_ch2_low=0x00002000 c_atg_system_ch3_high=0x000002FF c_atg_system_ch3_low=0x00000200
c_atg_system_ch4_high=0x000003FF c_atg_system_ch4_low=0x00000300 c_atg_system_ch5_high=0x000004FF c_atg_system_ch5_low=0x00000400
c_atg_system_cmd_max_retry=1024 c_atg_system_init=0 c_atg_system_init_addr_mif=axi_traffic_gen_0_addr.mem c_atg_system_init_ctrl_mif=axi_traffic_gen_0_ctrl.mem
c_atg_system_init_data_mif=axi_traffic_gen_0_data.mem c_atg_system_init_mask_mif=axi_traffic_gen_0_mask.mem c_atg_system_max_channels=0b00000000000000000000000000000010 c_atg_system_test=1
c_atg_system_test_max_clks=20000 c_axi_rd_addr_seed=0x5A5A c_axi_wr_addr_seed=0x7C9B c_axis1_has_tkeep=1
c_axis1_has_tstrb=1 c_axis2_has_tkeep=0 c_axis2_has_tstrb=0 c_axis_sparse_en=1
c_axis_tdata_width=32 c_axis_tdest_width=8 c_axis_tid_width=8 c_axis_tuser_width=8
c_baseaddr=0x00000000 c_family=spartan7 c_highaddr=0x0000FFFF c_m_axi_addr_width=32
c_m_axi_aruser_width=8 c_m_axi_awuser_width=8 c_m_axi_data_width=32 c_m_axi_thread_id_width=1
c_no_excl=0 c_raminit_addrram0_f=axi_traffic_gen_0_default_addrram.mem c_raminit_cmdram0_f=axi_traffic_gen_0_default_cmdram.mem c_raminit_cmdram1_f=NONE
c_raminit_cmdram2_f=NONE c_raminit_cmdram3_f=NONE c_raminit_paramram0_f=axi_traffic_gen_0_default_prmram.mem c_raminit_sram0_f=axi_traffic_gen_0_default_mstram.mem
c_read_only=0 c_repeat_count=254 c_s_axi_aruser_width=8 c_s_axi_awuser_width=8
c_s_axi_data_width=32 c_s_axi_id_width=1 c_strm_data_seed=0xABCD c_write_only=0
c_zero_invalid=1 core_container=NA iptotal=1 x_ipcorerevision=5
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_traffic_gen x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.0
clk_wiz_v6_0_3_0_0/1
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
xpm_memory_base/1
use_reset=true addr_width_a=9 addr_width_b=9 auto_sleep_time=0
byte_write_width_a=8 byte_write_width_b=32 cascade_height=0 clocking_mode=0
core_container=NA ecc_mode=0 iptotal=5 max_num_char=0
memory_optimization=true memory_primitive=0 memory_size=16384 memory_type=0
message_control=0 num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=1
p_enable_byte_write_b=0 p_max_depth_data=512 p_memory_opt=yes p_memory_primitive=auto
p_min_width_data=32 p_min_width_data_a=32 p_min_width_data_b=32 p_min_width_data_ecc=32
p_min_width_data_ldw=4 p_min_width_data_shft=32 p_num_cols_write_a=4 p_num_cols_write_b=1
p_num_rows_read_a=1 p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1
p_sdp_write_mode=yes p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0
p_width_addr_lsb_write_b=0 p_width_addr_read_a=9 p_width_addr_read_b=9 p_width_addr_write_a=9
p_width_addr_write_b=9 p_width_col_write_a=8 p_width_col_write_b=32 read_data_width_a=32
read_data_width_b=32 read_latency_a=1 read_latency_b=1 read_reset_value_a=0
read_reset_value_b=0 rst_mode_a=SYNC rst_mode_b=SYNC rsta_loop_iter=32
rstb_loop_iter=32 sim_assert_chk=0 use_embedded_constraint=0 use_mem_init=1
version=0 wakeup_time=0 write_data_width_a=32 write_data_width_b=32
write_mode_a=1 write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_utilization
clocking
bufgctrl_available=16 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=12.50
bufhce_available=24 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=4 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=8 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=2 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=50.00
plle2_adv_available=2 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=20 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=10 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=5.00
ramb18_available=20 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=5.00
ramb18e1_only_used=1 ramb36_fifo_available=10 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=114
fdre_functional_category=Flop & Latch fdre_used=2959 fdse_functional_category=Flop & Latch fdse_used=128
ibuf_functional_category=IO ibuf_used=18 lut1_functional_category=LUT lut1_used=27
lut2_functional_category=LUT lut2_used=380 lut3_functional_category=LUT lut3_used=623
lut4_functional_category=LUT lut4_used=453 lut5_functional_category=LUT lut5_used=482
lut6_functional_category=LUT lut6_used=856 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=364 muxf8_functional_category=MuxFx muxf8_used=182
obuf_functional_category=IO obuf_used=42 obuft_functional_category=IO obuft_used=16
ramb18e1_functional_category=Block Memory ramb18e1_used=1 rams64e_functional_category=Distributed Memory rams64e_used=464
srl16e_functional_category=Distributed Memory srl16e_used=185 srlc32e_functional_category=Distributed Memory srlc32e_used=264
slice_logic
f7_muxes_available=4000 f7_muxes_fixed=0 f7_muxes_used=364 f7_muxes_util_percentage=9.10
f8_muxes_available=2000 f8_muxes_fixed=0 f8_muxes_used=182 f8_muxes_util_percentage=9.10
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=464 lut_as_logic_available=8000 lut_as_logic_fixed=0
lut_as_logic_used=2334 lut_as_logic_util_percentage=29.18 lut_as_memory_available=2400 lut_as_memory_fixed=0
lut_as_memory_used=838 lut_as_memory_util_percentage=34.92 lut_as_shift_register_fixed=0 lut_as_shift_register_used=374
register_as_flip_flop_available=16000 register_as_flip_flop_fixed=0 register_as_flip_flop_used=3019 register_as_flip_flop_util_percentage=18.87
register_as_latch_available=16000 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=8000 slice_luts_fixed=0 slice_luts_used=3172 slice_luts_util_percentage=39.65
slice_registers_available=16000 slice_registers_fixed=0 slice_registers_used=3019 slice_registers_util_percentage=18.87
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=464 lut_as_logic_available=8000 lut_as_logic_fixed=0
lut_as_logic_used=2334 lut_as_logic_util_percentage=29.18 lut_as_memory_available=2400 lut_as_memory_fixed=0
lut_as_memory_used=838 lut_as_memory_util_percentage=34.92 lut_as_shift_register_fixed=0 lut_as_shift_register_used=374
lut_in_front_of_the_register_is_unused_fixed=374 lut_in_front_of_the_register_is_unused_used=795 lut_in_front_of_the_register_is_used_fixed=795 lut_in_front_of_the_register_is_used_used=436
register_driven_from_outside_the_slice_fixed=436 register_driven_from_outside_the_slice_used=1231 register_driven_from_within_the_slice_fixed=1231 register_driven_from_within_the_slice_used=1788
slice_available=2000 slice_fixed=0 slice_registers_available=16000 slice_registers_fixed=0
slice_registers_used=3019 slice_registers_util_percentage=18.87 slice_used=1083 slice_util_percentage=54.15
slicel_fixed=0 slicel_used=733 slicem_fixed=0 slicem_used=350
unique_control_sets_available=2000 unique_control_sets_fixed=2000 unique_control_sets_used=170 unique_control_sets_util_percentage=8.50
using_o5_and_o6_fixed=8.50 using_o5_and_o6_used=75 using_o5_output_only_fixed=75 using_o5_output_only_used=1
using_o6_output_only_fixed=1 using_o6_output_only_used=298
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7s15ftgb196-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=axi_emc_0_exdes -verilog_define=default::[not_specified]
usage
elapsed=00:00:24s hls_ip=0 memory_gain=569.805MB memory_peak=867.156MB