Project Statistics |
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PROP_FitterReportFormat=HTML |
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PROP_ManualCompileOrderImp=false |
PROP_MapExtraCostTable_spartan6=5 |
PROP_MapLUTCombining_spartan6=Auto |
PROP_MapLogicOptimization_spartan6=true |
PROP_MapPlacerCostTable_spartan6=100 |
PROP_MapPowerReduction_spartan6=Extra Effort |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/test_ddr3_memory_controller |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOpt=Area |
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PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
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PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2021-04-01T19:56:06 |
PROP_intWbtProjectID=194B1BB284779E991D15E1F8FA76BA86 |
PROP_intWbtProjectIteration=228 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_mapRegOrdering_spartan6=8 |
PROP_selectedSimRootSourceNode_behav=work.test_ddr3_memory_controller |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxMapAllowLogicOpt=true |
PROP_xilxMapSliceLogicInUnusedBRAMs=true |
PROP_xilxNgdbldIOPads=true |
PROP_xilxSynthAddBufg_spartan6=32 |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstAsynToSync=true |
PROP_xstAutoBRAMPacking=true |
PROP_xstCrossClockAnalysis=true |
PROP_xstNetlistHierarchy=Rebuilt |
PROP_xstOptimizeInsPrimtives=true |
PROP_xstReadCores=false |
PROPEXT_mapTimingMode_spartan6=Non Timing Driven |
PROP_AutoTop=false |
PROP_DevFamily=Spartan6 |
PROP_MapExtraEffort_spartan6=Continue on Impossible |
PROPEXT_xilxPARextraEffortLevel_spartan6=Continue on Impossible |
PROP_DevDevice=xc6slx16 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=ftg256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=Verilog |
FILE_COREGEN=11 |
FILE_UCF=1 |
FILE_VERILOG=10 |