test_ddr3_memory_controller Project Status (07/21/2021 - 20:39:12) | |||
Project File: | DDR_Xilinx_ISE.xise | Parser Errors: | No Errors |
Module Name: | test_ddr3_memory_controller | Implementation State: | Mapped |
Target Device: | xc6slx16-3ftg256 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Jul 10 15:54:41 2021 | ||||
Translation Report | Current | Sat Jul 10 15:54:44 2021 | ||||
Map Report | Current | Sat Jul 10 15:54:49 2021 | ||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Sat Aug 7 12:50:09 2021 | |
WebTalk Report | Current | Sat Aug 7 10:23:43 2021 | |
WebTalk Log File | Current | Sat Aug 7 10:23:44 2021 |