test_ddr3_memory_controller Project Status (07/21/2021 - 20:39:12)
Project File: DDR_Xilinx_ISE.xise Parser Errors: No Errors
Module Name: test_ddr3_memory_controller Implementation State: Mapped
Target Device: xc6slx16-3ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jul 10 15:54:41 2021   
Translation ReportCurrentSat Jul 10 15:54:44 2021   
Map ReportCurrentSat Jul 10 15:54:49 2021   
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentSat Aug 7 12:50:09 2021
WebTalk ReportCurrentSat Aug 7 10:23:43 2021
WebTalk Log FileCurrentSat Aug 7 10:23:44 2021

Date Generated: 08/07/2021 - 14:30:14