serdes_1_to_n_data_ddr_s8_diff Project Status (07/11/2021 - 13:06:52)
Project File: DDR_Xilinx_ISE.xise Parser Errors: No Errors
Module Name: ddr3_memory_controller Implementation State: Placed and Routed (Failed)
Target Device: xc6slx16-3ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jul 10 15:53:31 2021   
Translation ReportCurrentSat Jul 10 15:53:34 2021   
Map ReportCurrentSat Jul 10 15:53:39 2021   
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Jul 11 13:02:47 2021
WebTalk ReportOut of DateSun Jul 11 12:08:10 2021
WebTalk Log FileOut of DateSun Jul 11 12:08:11 2021

Date Generated: 07/11/2021 - 13:06:52