serdes_1_to_n_data_ddr_s8_diff Project Status (07/11/2021 - 13:06:52) | |||
Project File: | DDR_Xilinx_ISE.xise | Parser Errors: | No Errors |
Module Name: | ddr3_memory_controller | Implementation State: | Placed and Routed (Failed) |
Target Device: | xc6slx16-3ftg256 |
|
|
Product Version: | ISE 14.7 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Jul 10 15:53:31 2021 | ||||
Translation Report | Current | Sat Jul 10 15:53:34 2021 | ||||
Map Report | Current | Sat Jul 10 15:53:39 2021 | ||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Sun Jul 11 13:02:47 2021 | |
WebTalk Report | Out of Date | Sun Jul 11 12:08:10 2021 | |
WebTalk Log File | Out of Date | Sun Jul 11 12:08:11 2021 |