test_ddr3_memory_controller Project Status (07/10/2021 - 15:54:49) | |||
Project File: | DDR_Xilinx_ISE.xise | Parser Errors: | No Errors |
Module Name: | serdes_1_to_n_data_ddr_s8_diff | Implementation State: | Mapped (Failed) |
Target Device: | xc6slx16-3ftg256 |
|
X 2 Errors (0 new) |
Product Version: | ISE 14.7 |
|
2 Warnings (1 new) |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Jul 10 15:54:41 2021 | 0 | 2 Warnings (1 new) | 1 Info (1 new) | |
Translation Report | Current | Sat Jul 10 15:54:44 2021 | 0 | 0 | 0 | |
Map Report | Current | Sat Jul 10 15:54:49 2021 | X 2 Errors (0 new) | 0 | 6 Infos (2 new) | |
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Sat Jul 10 15:12:41 2021 | |
WebTalk Log File | Out of Date | Sat Jul 10 15:12:42 2021 |