test_ddr3_memory_controller Project Status (07/10/2021 - 15:54:49)
Project File: DDR_Xilinx_ISE.xise Parser Errors: No Errors
Module Name: serdes_1_to_n_data_ddr_s8_diff Implementation State: Mapped (Failed)
Target Device: xc6slx16-3ftg256
  • Errors:
X 2 Errors (0 new)
Product Version:ISE 14.7
  • Warnings:
2 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jul 10 15:54:41 202102 Warnings (1 new)1 Info (1 new)
Translation ReportCurrentSat Jul 10 15:54:44 2021000
Map ReportCurrentSat Jul 10 15:54:49 2021X 2 Errors (0 new)06 Infos (2 new)
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateSat Jul 10 15:12:41 2021
WebTalk Log FileOut of DateSat Jul 10 15:12:42 2021

Date Generated: 07/10/2021 - 15:54:49