test_ddr3_memory_controller Project Status (07/08/2021 - 18:55:13)
Project File: DDR_Xilinx_ISE.xise Parser Errors: No Errors
Module Name: ddr3_memory_controller Implementation State: Translated (Failed)
Target Device: xc6slx16-3ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jun 19 15:29:56 2021   
Translation ReportOut of DateMon May 24 20:10:50 2021   
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue Jun 22 11:20:20 2021
WebTalk Log FileOut of DateTue Jun 22 11:20:21 2021

Date Generated: 07/08/2021 - 18:55:14