serdes_1_to_n_data_ddr_s8_diff Project Status (07/10/2021 - 17:41:41)
Project File: DDR_Xilinx_ISE.xise Parser Errors: No Errors
Module Name: test_ddr3_memory_controller Implementation State: Placed and Routed (Failed)
Target Device: xc6slx16-3ftg256
  • Errors:
X 1 Error (0 new)
Product Version:ISE 14.7
  • Warnings:
635 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
X 484 Signals Not Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 160 18,224 1%  
    Number used as Flip Flops 160      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 330 9,112 3%  
    Number used as logic 319 9,112 3%  
        Number using O6 output only 230      
        Number using O5 output only 42      
        Number using O5 and O6 47      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 11      
        Number with same-slice register load 8      
        Number with same-slice carry load 3      
        Number with other load 0      
Number of occupied Slices 139 2,278 6%  
Number of MUXCYs used 60 4,556 1%  
Number of LUT Flip Flop pairs used 365      
    Number with an unused Flip Flop 216 365 59%  
    Number with an unused LUT 35 365 9%  
    Number of fully used LUT-FF pairs 114 365 31%  
    Number of unique control sets 9      
    Number of slice register sites lost
        to control set restrictions
48 18,224 1%  
Number of bonded IOBs 52 186 27%  
    Number of LOCed IOBs 52 52 100%  
    IOB Flip Flops 45      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 4 16 25%  
    Number used as BUFGs 4      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 3 248 1%  
    Number used as ILOGIC2s 3      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 4 248 1%  
    Number used as IODELAY2s 4      
    Number used as IODRP2s 0      
    Number used as IODRP2_MCBs 0      
Number of OLOGIC2/OSERDES2s 22 248 8%  
    Number used as OLOGIC2s 22      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: X 484 Signals Not Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Jul 10 17:41:23 20210445 Warnings (0 new)12 Infos (0 new)
Translation ReportCurrentSat Jul 10 17:41:27 20210170 Warnings (0 new)0
Map ReportCurrentSat Jul 10 17:41:37 2021008 Infos (0 new)
Place and Route ReportCurrentSat Jul 10 17:41:41 2021X 1 Error (0 new)20 Warnings (1 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of DateSat Jul 10 15:58:18 2021005 Infos (1 new)
Bitgen ReportOut of DateSat Jul 10 15:56:46 2021000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateSat Jul 10 15:56:47 2021
WebTalk Log FileOut of DateSat Jul 10 15:56:48 2021

Date Generated: 07/10/2021 - 17:41:41