test_ddr3_memory_controller Project Status (07/08/2021 - 18:55:13) | |||
Project File: | DDR_Xilinx_ISE.xise | Parser Errors: | No Errors |
Module Name: | ddr3_memory_controller | Implementation State: | Translated (Failed) |
Target Device: | xc6slx16-3ftg256 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Jun 19 15:29:56 2021 | ||||
Translation Report | Out of Date | Mon May 24 20:10:50 2021 | ||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Tue Jun 22 11:20:20 2021 | |
WebTalk Log File | Out of Date | Tue Jun 22 11:20:21 2021 |