Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedSat Aug 15 12:40:18 2020 os_platformWIN64
product_versionVivado v2020.1 (64-bit) project_idb8664478a264441f8d5944092515a3e9
project_iteration7 random_ida32790a03520543595693428a9eadc33
registration_id211373645_0_0_435 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagefgg676 target_speed-2
tool_flowVivado

user_environment
cpu_nameAMD Phenom(tm) II X4 955 Processor cpu_speed3214 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
abstractfileview_reload=2 basedialog_apply=5 basedialog_cancel=21 basedialog_ok=229
basedialog_yes=3 basereporttab_rerun=1 cmdmsgdialog_ok=10 cmdmsgdialog_open_messages_view=1
coretreetablepanel_core_tree_table=12 expreporttreepanel_exp_report_tree_table=21 expruntreepanel_exp_run_tree_table=1 filesetpanel_file_set_panel_tree=321
findandreplacealldialog_find=2 findinfilesview_root=6 flownavigatortreepanel_flow_navigator_tree=53 fpgachooser_family=2
fpgachooser_fpga_table=6 fpgachooser_package=3 fpgachooser_speed=3 gettingstartedview_open_project=4
hardwaretreepanel_hardware_tree_table=6 hcodeeditor_blank_operations=2 hcodeeditor_commands_to_fold_text=2 hcodeeditor_diff_with=2
hcodeeditor_search_text_combo_box=1 hinputhandler_indent_selection=1 mainmenumgr_checkpoint=17 mainmenumgr_constraints=2
mainmenumgr_edit=6 mainmenumgr_export=10 mainmenumgr_file=38 mainmenumgr_import=3
mainmenumgr_ip=16 mainmenumgr_project=18 mainmenumgr_reports=2 mainmenumgr_text_editor=14
mainmenumgr_tools=8 mainmenumgr_unselect_type=8 mainmenumgr_view=12 mainmenumgr_window=16
mainwinmenumgr_layout=4 mainwinmenumgr_load=1 msgtreepanel_message_severity=2 msgtreepanel_message_view_tree=47
msgview_error_messages=2 msgview_information_messages=5 msgview_warning_messages=1 netlisttreeview_netlist_tree=6
numjobschooser_number_of_jobs=1 pacommandnames_auto_connect_target=5 pacommandnames_auto_update_hier=1 pacommandnames_close_project=16
pacommandnames_core_gen=1 pacommandnames_fileset_window=1 pacommandnames_find_in_files=2 pacommandnames_open_hardware_manager=2
pacommandnames_project_summary=1 pacommandnames_properties_window=2 pacommandnames_recustomize_core=1 pacommandnames_reports_window=12
pacommandnames_run_bitgen=9 pacommandnames_run_implementation=5 pacommandnames_save_design=4 pacommandnames_toggle_view_nav=2
pacommandnames_upgrade_ip=32 paviews_code=8 paviews_ip_catalog=2 paviews_package=5
paviews_par_report=2 paviews_project_summary=5 programdebugtab_open_target=5 programdebugtab_program_device=6
programfpgadialog_program=6 programfpgadialog_specify_bitstream_file=6 project_save_project_as=1 projectnamechooser_choose_project_location=2
projectnamechooser_create_project_subdirectory=2 projectnamechooser_project_name=2 projecttab_reload=2 propertiesview_next_object=1
rdicommands_copy=1 rdicommands_custom_commands=2 rdicommands_properties=1 rdicommands_run_script=2
rdicommands_save_file=38 rdicommands_undo=3 reportipstatusinfodialog_report_ip_status=2 rungadget_show_error=3
rungadget_show_error_and_critical_warning_messages=10 rungadget_show_warning_and_error_messages_in_messages=2 saveprojectutils_cancel=1 saveprojectutils_save=1
settingsprojectgeneralpage_choose_device_for_your_project=3 signaltreepanel_signal_tree_table=86 simpleoutputproductdialog_generate_output_products_immediately=11 simpleoutputproductdialog_output_product_tree=4
srcmenu_ip_documentation=36 statemonitor_reset_run=1 syntheticagettingstartedview_recent_projects=15 syntheticastatemonitor_cancel=6
taskbanner_close=10 tclconsoleview_tcl_console_code_editor=3 touchpointsurveydialog_remind_me_later=1 touchpointsurveydialog_yes=1
java_command_handlers
addsources=1 autoconnecttarget=5 closeproject=17 coreview=2
customizecore=1 editpaste=1 editproperties=1 editundo=1
fileexit=2 launchprogramfpga=6 openhardwaremanager=5 openproject=4
projectsummary=1 recustomizecore=27 reportclocknetworks=1 reportipstatus=2
reporttimingsummary=1 runbitgen=7 runimplementation=29 runscript=1
runsynthesis=31 savedesign=4 saveprojectas=1 showview=42
simulationcompilelibraries=1 toggleviewnavigator=2 toolssettings=6 ui.views.c.h.f=2
upgradeip=32 viewlayoutcmd=1 viewtaskrtlanalysis=5
other_data
guimode=19
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_4 currentsynthesisrun=synth_3
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=11 export_simulation_ies=11
export_simulation_modelsim=11 export_simulation_questa=11 export_simulation_riviera=11 export_simulation_vcs=11
export_simulation_xsim=11 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=29 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=9 totalsynthesisruns=8

unisim_transformation
post_unisim_transformation
bufg=7 carry4=277 dsp48e1=37 fdce=26
fdpe=26 fdre=1677 fdse=43 gnd=148
ibuf=19 lut1=367 lut2=469 lut3=348
lut4=449 lut5=413 lut6=571 mmcme2_adv=2
muxf7=3 obuf=8 obufds=4 obuft=1
ramb18e1=3 ramb36e1=121 srl16e=21 vcc=140
pre_unisim_transformation
bufg=7 carry4=277 dsp48e1=37 fdce=26
fdpe=26 fdre=1677 fdse=43 gnd=148
ibuf=19 iobuf=1 lut1=367 lut2=469
lut3=348 lut4=449 lut5=413 lut6=571
mmcme2_adv=2 muxf7=3 obuf=8 obufds=4
ramb18e1=3 ramb36e1=121 srl16e=21 vcc=140

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=121 bram_ports_newly_gated=121 bram_ports_total=248 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=1758 srls_augmented=0
srls_newly_gated=0 srls_total=21

ip_statistics
axi_uartlite/1
c_baudrate=9600 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=25000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=25 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_4/1
c_addra_width=18 c_addrb_width=18 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=40 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 23.211502 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=1 c_has_mem_output_regs_b=1 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=ram.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=262144 c_read_depth_b=262144 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=5 c_read_width_b=5 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=1 c_web_width=1
c_write_depth_a=262144 c_write_depth_b=262144 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=5 c_write_width_b=5 c_xdevicefamily=artix7 core_container=false
iptotal=3 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v6_0_5_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v6_0_5_0_0/2
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_1
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
fifo_generator_v13_2_5/1
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=1 c_axi_len_width=8 c_axi_lock_width=1 c_axi_ruser_width=1
c_axi_type=1 c_axi_wuser_width=1 c_axis_tdata_width=8 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tkeep_width=1 c_axis_tstrb_width=1 c_axis_tuser_width=4
c_axis_type=0 c_common_clock=0 c_count_type=0 c_data_count_width=12
c_default_value=BlankString c_din_width=8 c_din_width_axis=1 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_wach=1 c_din_width_wdch=64 c_din_width_wrch=2
c_dout_rst_val=0 c_dout_width=8 c_en_safety_ckt=1 c_enable_rlocs=0
c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0 c_error_injection_type_rach=0
c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0 c_error_injection_type_wrch=0
c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0 c_has_almost_full=0
c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0 c_has_axi_id=0
c_has_axi_rd_channel=1 c_has_axi_ruser=0 c_has_axi_wr_channel=1 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=1
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=1 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_power_saving_mode=0 c_preload_latency=1
c_preload_regs=0 c_prim_fifo_type=4kx9 c_prim_fifo_type_axis=1kx18 c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_negate_val=3
c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_full_thresh_assert_val=4093
c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=4092 c_prog_full_type=0
c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0 c_rd_data_count_width=12
c_rd_depth=4096 c_rd_freq=1 c_rd_pntr_width=12 c_rdch_type=0
c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_select_xpm=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_use_pipeline_reg=0
c_valid_low=0 c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0
c_wr_data_count_width=12 c_wr_depth=4096 c_wr_depth_axis=1024 c_wr_depth_rach=16
c_wr_depth_rdch=1024 c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16
c_wr_freq=1 c_wr_pntr_width=12 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_response_latency=1 c_wrch_type=0 core_container=false iptotal=1
x_ipcorerevision=5 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=fifo_generator
x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=13.2
hls_ip_2017_4/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=1
hls_input_float=0 hls_input_part=xc7a200tsbg484-1 hls_input_type=cxx hls_syn_clock=9.326000
hls_syn_dsp=33 hls_syn_ff=2165 hls_syn_lat=768975 hls_syn_lut=2673
hls_syn_mem=3 hls_syn_tpt=none iptotal=1
xpm_cdc_gray/1
core_container=NA dest_sync_ff=2 init_sync_ff=0 iptotal=2
reg_output=1 sim_assert_chk=0 sim_lossless_gray_chk=0 version=0
width=12
xpm_cdc_single/1
core_container=NA dest_sync_ff=5 init_sync_ff=0 iptotal=2
sim_assert_chk=0 src_input_reg=0 version=0
xpm_cdc_sync_rst/1
core_container=NA def_val=1'b1 dest_sync_ff=5 init=1
init_sync_ff=0 iptotal=2 sim_assert_chk=0 version=0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
dpip-1=10 dpop-1=13 dpop-2=21 plck-23=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=8 bufgctrl_util_percentage=25.00
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=2 mmcme2_adv_util_percentage=33.33
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=37 dsps_available=240 dsps_fixed=0 dsps_used=37
dsps_util_percentage=15.42
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=122.5 block_ram_tile_util_percentage=90.74
ramb18_available=270 ramb18_fixed=0 ramb18_used=3 ramb18_util_percentage=1.11
ramb18e1_only_used=3 ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=121
ramb36_fifo_util_percentage=89.63 ramb36e1_only_used=121
primitives
bufg_functional_category=Clock bufg_used=8 carry4_functional_category=CarryLogic carry4_used=277
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=37 fdce_functional_category=Flop & Latch fdce_used=38
fdpe_functional_category=Flop & Latch fdpe_used=26 fdre_functional_category=Flop & Latch fdre_used=1661
fdse_functional_category=Flop & Latch fdse_used=43 ibuf_functional_category=IO ibuf_used=19
lut1_functional_category=LUT lut1_used=138 lut2_functional_category=LUT lut2_used=528
lut3_functional_category=LUT lut3_used=347 lut4_functional_category=LUT lut4_used=510
lut5_functional_category=LUT lut5_used=472 lut6_functional_category=LUT lut6_used=555
mmcme2_adv_functional_category=Clock mmcme2_adv_used=2 muxf7_functional_category=MuxFx muxf7_used=3
obuf_functional_category=IO obuf_used=8 obufds_functional_category=IO obufds_used=4
obuft_functional_category=IO obuft_used=1 ramb18e1_functional_category=Block Memory ramb18e1_used=3
ramb36e1_functional_category=Block Memory ramb36e1_used=121 srl16e_functional_category=Distributed Memory srl16e_used=21
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=3 f7_muxes_util_percentage=<0.01
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=1992 lut_as_logic_util_percentage=3.14 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=13 lut_as_memory_util_percentage=0.07 lut_as_shift_register_fixed=0 lut_as_shift_register_used=13
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=1768 register_as_flip_flop_util_percentage=1.39
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=2005 slice_luts_util_percentage=3.16
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=1768 slice_registers_util_percentage=1.39
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=1992 lut_as_logic_util_percentage=3.14 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=13 lut_as_memory_util_percentage=0.07 lut_as_shift_register_fixed=0 lut_as_shift_register_used=13
lut_in_front_of_the_register_is_unused_fixed=13 lut_in_front_of_the_register_is_unused_used=526 lut_in_front_of_the_register_is_used_fixed=526 lut_in_front_of_the_register_is_used_used=247
register_driven_from_outside_the_slice_fixed=247 register_driven_from_outside_the_slice_used=773 register_driven_from_within_the_slice_fixed=773 register_driven_from_within_the_slice_used=995
slice_available=15850 slice_fixed=0 slice_registers_available=126800 slice_registers_fixed=0
slice_registers_used=1768 slice_registers_util_percentage=1.39 slice_used=957 slice_util_percentage=6.04
slicel_fixed=0 slicel_used=565 slicem_fixed=0 slicem_used=392
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_used=100 unique_control_sets_util_percentage=0.63
using_o5_and_o6_fixed=0.63 using_o5_and_o6_used=8 using_o5_output_only_fixed=8 using_o5_output_only_used=5
using_o6_output_only_fixed=5 using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7a100tfgg676-2 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=top -verilog_define=default::[not_specified]
usage
elapsed=00:02:01s hls_ip=1 memory_gain=244.520MB memory_peak=1265.656MB