Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Simultaneous read and write in memory

F

fragnen

Full Member level 4
Joined
Apr 3, 2019
Messages
208
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,458
What phenomenon happens when a read and write operation is requested at the same clock cycle for a single port memory?
 
Sort by date Sort by votes
When a read and write operation is requested at the same clock cycle for a single-port memory, a conflict known as a "read-write conflict" or "read-modify-write conflict" can occur. As a solution, the conflicting requests can be queued or buffered temporarily until the memory becomes available to process the pending operation.
 
Upvote 0 Downvote
I haven't seen any single port memory which can do simultaneous read and write in the same cycle. There's always a control signal input to indicate whether it is a read or write operation for the particular clock cycle. Read-modify-write is a higher-level operation, it involves multiple cycles of memory access.
 
Upvote 0 Downvote
A single port memory with separate read and write data lines can perform simultaneous read and write. Specification may e.g. require old data to appear at the read port. Obviously the behaviour depends on internal memory structure, registering of signals etc.
 
Upvote 0 Downvote
tepalia02 said:
When a read and write operation is requested at the same clock cycle for a single-port memory, a conflict known as a "read-write conflict" or "read-modify-write conflict" can occur. As a solution, the conflicting requests can be queued or buffered temporarily until the memory becomes available to process the pending operation.
Click to expand...
Will there be inbuilt circuitry in memory using which conflicting requests can be queued?

Otherwise, is it that we need to design such logic which will be external to the memory so that that logic can queue conflicting requests?
 
Upvote 0 Downvote
I presume you mean for SRAMs, right? Single port SRAMs have a mesh of vertical bitlines and horizontal wordlines. Bitlines will decode perhaps the lower address bits and the wordlines will decode the upper bits. Where the two meet you get an access. Actually you will use perhaps 8 bitlines at once and 1 wordline to read one byte or more bitlines if you want say 32 bits.

Dual port SRAMs do this by doubling the number of bitlines and wordlines, one set for reading and one set for writing. If you happen to address the exact same guy for reading and writing you get some undefined intermediary value. Some FPGAs and SRAMs have a bypass logic built-in that detects this dual access and when they see this they copy your write data to the memory and to the output pins.

For single port memories this is not possible as you cannot power up the array for both reads and writes. This is because the voltages applied are different. It depends on the actual technology used, and I have not worked on memory design in years, but, if I recall it right, for writing you would take the bitline to VDD. For reading you would take it to a much lower voltage, like VDD/2 and then use a sense amp to measure the current. So, if you tried to mix the two you might be able to write the data but you would get some corrupted read value.

On most SRAMs this is not even possible, the block will not allow you to raise read enable and write enable together. In many SRAMs do not even have a way to do that as in these write-enable is CS_n=0 and WE_n=0 while read is CS_n=0 and WE_n=1, so they are mutually exclusive.

So, yes, I have never seen a memory that already came with this interface, and I think it is because there are multiple ways to do it, depending on your design requirerments. So you need a wrapper. Perhaps you could say both the reader block and the writer block raise a signal and they wait for some ready signal to go high to take the request down, like on a AXI ready/valid style interface. Then you decide which you do first, reads first, writes first, or something fancier. Another way would be to store the write request locally, like in a single position fifo, and write it when the memory is free. This works fine as long as you know the requests are sporadic.
 
Upvote 0 Downvote
FvM said:
A single port memory with separate read and write data lines can perform simultaneous read and write. Specification may e.g. require old data to appear at the read port. Obviously the behaviour depends on internal memory structure, registering of signals etc.
Click to expand...
Maybe I’ve just missed it, but I’ve never seen a SINGLE port RAM with separate read and write data busses.
 
Upvote 0 Downvote
Some don't even have separate read and write ports, instead have a single w signal that is active 1 for write, 0 is read.
 
Upvote 0 Downvote
barry said:
Maybe I’ve just missed it, but I’ve never seen a SINGLE port RAM with separate read and write data busses.
Click to expand...
Generally the case with FPGA block ram with separate (unidirectional) read and write port.

A problem of the initial question is that it doesn't specify details, e.g. asynchronous or synchronous RAM operation.
 
Upvote 0 Downvote
glennramalho said:
I presume you mean for SRAMs, right? Single port SRAMs have a mesh of vertical bitlines and horizontal wordlines. Bitlines will decode perhaps the lower address bits and the wordlines will decode the upper bits. Where the two meet you get an access. Actually you will use perhaps 8 bitlines at once and 1 wordline to read one byte or more bitlines if you want say 32 bits.

Dual port SRAMs do this by doubling the number of bitlines and wordlines, one set for reading and one set for writing. If you happen to address the exact same guy for reading and writing you get some undefined intermediary value. Some FPGAs and SRAMs have a bypass logic built-in that detects this dual access and when they see this they copy your write data to the memory and to the output pins.

For single port memories this is not possible as you cannot power up the array for both reads and writes. This is because the voltages applied are different. It depends on the actual technology used, and I have not worked on memory design in years, but, if I recall it right, for writing you would take the bitline to VDD. For reading you would take it to a much lower voltage, like VDD/2 and then use a sense amp to measure the current. So, if you tried to mix the two you might be able to write the data but you would get some corrupted read value.

On most SRAMs this is not even possible, the block will not allow you to raise read enable and write enable together. In many SRAMs do not even have a way to do that as in these write-enable is CS_n=0 and WE_n=0 while read is CS_n=0 and WE_n=1, so they are mutually exclusive.

So, yes, I have never seen a memory that already came with this interface, and I think it is because there are multiple ways to do it, depending on your design requirerments. So you need a wrapper. Perhaps you could say both the reader block and the writer block raise a signal and they wait for some ready signal to go high to take the request down, like on a AXI ready/valid style interface. Then you decide which you do first, reads first, writes first, or something fancier. Another way would be to store the write request locally, like in a single position fifo, and write it when the memory is free. This works fine as long as you know the requests are sporadic.
Click to expand...

Does not it mean that you are suggesting that we need to design such logic which will be external to the memory? Your last paragraph mainly states that. Please answer. Thanks for your reply.
--- Updated ---

FvM said:
A problem of the initial question is that it doesn't specify details, e.g. asynchronous or synchronous RAM operation.
Click to expand...

The question in post number 1 includes both synchronous and asynchronous memories.
 
Upvote 0 Downvote
fragnen said:
Does not it mean that you are suggesting that we need to design such logic which will be external to the memory? Your last paragraph mainly states that. Please answer. Thanks for your reply.
--- Updated ---



The question in post number 1 includes both synchronous and asynchronous memories.
Click to expand...
Hi,

perhaps I explained it poorly;

like it was mentioned we have 2 port memories, which we have one port for writing, and one for reading. These can be synchronous or not, in hard IPs they are usualy asynchronous but in FPGA memories you have both. Synchronous meaning both ports use the same clock, asynchronous meaning each port has one clock.

Then we have one port memories. These, there is only one address input, usually one enable, perhaps if it is low it is write and high it is read or the reverse. Of course these will have just one clock.

Now the question is what happens if we have two requests at the same time.

On a 2-port memories were built to take two requests at the same time, one read and one write. As I mentioned, the array has two paths to the cells, so one can read and one can write. The only concern is if you happend to try to read and write to the exact same address at the same time. Some memory IPs in this case will return you garbage (example: create a 2-port memory in Quartus and set ram_style attribute to "no_rw_check"), some memory IPs will detect this and the read will bypass the array and give you the write data while the data is beign written to the array (in quartus do the same, just don't set that attribute and you get a memory with this bypass). If you are concerned with this situation, just read the datasheet of the memory to see what happens if you have a read and a write to the same address at the same time.

Now, on a 1-port memory, we only have one port, so what do we do if we have two requests at the same time. We only have one port. We then need some kind of handshake mechanism to make sure we can arbitrate who goes first and who waits. There are multiple ways to do that.

  1. If we know reads and writes are rare, we could have a small FSM that did: if I see a read and a write in the same cycle, I will store the write, do the read, and when the read finishes, I will do the write. The other blocks do not need to be aware of this delay.
  2. If we do not know how often reads and writes arrive, we then have to do a proper handshake. For example, each block that wants to do the access it will place the request and raise say a valid line. The valid line must remain high until it receives a ready signal. If it is a read, the read value will return with ready.
And if we have a 2-port memory with multiple writers, or multiple readers. Then you would have to do some arbitration on the side with multiple guys. Because 2-port SRAMs can only do one read and one write.

hope this is easier to understand
 
Upvote 0 Downvote

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top