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First check if all the flip-flops you expect to appear on the netlist are actually there. Synthesis will eliminate any flops that it believes are useless, and that will most likely break your design.
Second, gate-level sim is an art form. You gotta make sure you have the right libraries that...
If your code is really this simple, I would use a script to generate it externally. verilog generate statements have limitations and it can be annoying to use.
There are some problems with your logic... you are not consistently using reset:
None of these flops is being assigned to zero on gate level because initial assignments are not honored. Your synthesis tool must have warned you about this.
If this is really done, and I don't know if its done, it would be a one-off thing. No new PDK would be generated. And the samples would probably be more prone to defects because the process is pushed to its limits, outside of the comfort zone of mass production.
I still don't understand the question. You can think of SS as a contract between you and the foundry. You should not be getting any chips that perform worse than SS in a mature process. Anything near TT, near FF, or above FF, is icing on the cake. I don't see an immediate need for testing or...
This is one way, with calibredrv. But it is not very intuitive. digital designers want to see the errors in their design environments, like Innovus and ICC. See oratie's aswer above.
I don't know how to help you. If the only information you can give is "it doesn't work", it is of no help. Did you check logs? Did you check folders to see if the gds files were generated? Did you debug at all? Did you try switches at random? Have you tried to run fill on a small design first to...
You can have perfectly correct modules and still make mistakes in top-level connections. LVS would show these mistakes somewhere, not necessarily on the top level when you include everything. Debug debug debug. Consider adding one block at a time if possible.
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