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omar97's latest activity

  • O
    omar97 replied to the thread ESD.
    OK, I will add bonds and check again. Thanks
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    omar97 replied to the thread ESD.
    I have a ring of pads that containg IO pads, power pads, filler pads, and corner pads. In future work we will add IO bonds.
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    omar97 replied to the thread ESD.
    In documentation, ESD on IO pads can be waivable but it is not state for corner pads. I have ESD violations only on lower left pad, so...
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    omar97 replied to the thread ESD.
    Thank you for your advice 😊
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    omar97 posted the thread ESD in ASIC Design Methodologies and Tools (Digital).
    Hello all, I am using TSMC 65nm technology, I finished the design and when checking DRC thre is only one rule violated ESD.22g only on...
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    omar97 replied to the thread read_gds.
    Sir, I said I open gds on klayout and don't see macro layout, so I try to open it I icc2 as klayout doesn't see any error messages. In...
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    omar97 replied to the thread read_gds.
    I know that. But I just want to know what is the error.
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    omar97 replied to the thread read_gds.
    Ic compiler 2
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    omar97 posted the thread read_gds in ASIC Design Methodologies and Tools (Digital).
    hi all, i have a problem in writing gds of whole chip that consist of memory macros and STD. the problem is the mapping of macros isn't...
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    omar97 replied to the thread macro mapping.
    Yes, it gives me a warning massage: the user specified view layout for lib_cell ....... is not available
  • O
    omar97 replied to the thread macro mapping.
    Yes, it has all layers. I can see it in gds viewer (klayout) 1716275666 Yes it is a blockage in fram view. But I want to get real shape...
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    omar97 replied to the thread macro mapping.
    Actually, there no errors or warning message during write_gds Icc2 maps macros as it is a wide sheet of metal (about 75 um wide). I...
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    omar97 replied to the thread macro mapping.
    Yes, I did exactly as you say As example Command : write_gds ....... - merge_files memory.gds
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    omar97 posted the thread macro mapping in ASIC Design Methodologies and Tools (Digital).
    hello all, i have a problem in macro mapping. i am using icc2 tool (synopsys). i have a memory in design (SRAM macros). i generated it...
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    omar97 replied to the thread problem in metal fill with ICV.
    i use this options and everything is ok. signoff_create_metal_fill -track_fill generic -select_layers M2 -fill_all_tracks true...
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